Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-06-01
2004-02-24
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000, C345S209000, C345S100000
Reexamination Certificate
active
06697038
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a signal transfer system having a plurality of signal input-output sections that are connected with each other in a cascade manner, a display panel drive apparatus, and a display apparatus using such a display panel drive apparatus, the respective system and apparatuses being provided in a drive apparatus of a liquid crystal display apparatus, for example.
BACKGROUND OF THE INVENTION
Recently, a liquid crystal display apparatus of an active matrix type has been widely used as a display apparatus for a personal computer of such as a desk top type or a notebook type or as every kind of monitor. The liquid crystal display apparatus of an active matrix type is provided with an active matrix substrate on which a plurality of pixels electrodes are provided in a matrix manner, an opposing substrate on which an opposing electrode is provided, and a liquid crystal layer provided between the active matrix substrate and the opposing substrate.
The active matrix substrate is provided with switching devices such as TFTs (Thin Film Transistors) for selectively driving the pixel electrodes. The switching devices are connected with the respective pixel electrodes. The TFT has a gate electrode that is connected with a gate bus line and a source electrode that is connected with a source bus line. The gate bus line and the source bus line are provided so as to extend orthogonal to each other around the respective pixel electrodes that are provided in a matrix manner. When the gate signal is inputted via the gate bus line, the TFT is driven and controlled, and concurrently, a data signal (display signal) is inputted into the pixel electrode via the TFT during the driving of the TFT in response to a signal sent via the source bus line. This allows that an electric field is generated between the pixel electrode and the opposing electrode. The electric field causes the alignment state to change so as to display the image.
Each source bus line is connected with the source driver which outputs the data signal to each source bus line. The source drivers are provided in accordance with the number of the source bus lines. Each source driver receives the data signal to be sent to the source bus line associated with the source driver via a timing controller.
The data transfer to the source driver is carried out in response to the signals such as a start pulse input signal SPin, a data signal DATA, and a start pulse output signal SPout.
FIG. 17
is a time chart showing the respective signals in the nth source driver n and the (n+1)th source driver n+1. This example deals with the case where each source driver has 300 outputs. When it is assumed that the data of each color component of R, G, and B for 1 block are fetched, it appears that the sampling of the data corresponding to 100 clocks is carried out with respect to a single source driver.
After receiving the start pulse input signal SPin, each source driver starts to carry out the data sampling in response to the next clock. When the data sampling corresponding to 100 clocks is completed, the start pulse output signal SPout is sent to the source driver of the next stage. The start pulse output signal SPout is sent to the source driver of the next stage as a start pulse input signal SPin. This allows the source driver of the next stage to carry out a data sampling in a manner similar to the above-described procedure.
As to the entire liquid crystal panel, in the case of SVGA having 800×600 pixels, 8(800÷100(clocks)) source drivers are connected with each other in a cascade manner.
FIG. 18
is an explanatory diagram showing the schematic connecting state of the source drivers STAB
1
through STAB
8
. As shown in
FIG. 18
, the data signal DATA and the latch strobe signal LS are sent to the respective source drivers STAB
1
through STAB
8
in parallel. The start pulse input signal SPin is sent to the source driver STAB
1
. The source driver STAB
2
and its succeeding source drivers receive the start pulse SPout from the source driver of the previous stage as the start pulse input signal SPin.
In the case where the data samplings of the source drivers STAB
1
through STAB
8
are completed in the above-described manner, when the latch strobe signal is sent to the respective source drivers STAB
1
through STAB
8
, an analog voltage corresponding to all the sampling data that correspond to 1 line is outputted from the output terminals of the respective source drivers STAB
1
through STAB
8
. A voltage corresponding to the data signal is applied to each of the pixel electrodes on the line that has been selected by the gate signal.
In the timing chart shown in
FIG. 17
, the operating frequency of the start pulse input signal SPin the data signal DATA and the start pulse output signal SPout is coincident with the clock frequency fck. For example, in the case of SVGA, the clock frequency fck is equal to 40 MHz (clock period Tck=1/fck=25(ns)) according to the VESA (The Video Electronics Standards Association) standard, while in the case of XGA, the clock frequency fck is equal to 65 MHz (clock period Tck=15.38(ns)).
FIG. 19
shows the timing charts of the clock signal and the data signal DATA, respectively. Note that it is assumed that the data sampling is carried out in synchronization with the rising (see time Tu in
FIG. 19
) of the clock signal. During the time period between the time that is 1.5(ns) to the time Tu and the time when 1(ns) is elapsed after the time Tu, it is necessary that the data signal DATA be settled. Unless otherwise, it is not possible to correctly carry out the data sampling. The above-described time 1.5(ns) is referred to as a data setup time tsu, and the time 1(ns) is referred to as a data hold time th.
FIGS.
20
(
a
) and
20
(
b
) show examples of time charts of the relation between the clock signal and 1 bit of the data. In FIG.
20
(
a
), at the time that is 0.5(ns) to the rising of the clock signal, the 1 bit of the data falls down to “L” from “H”. In this case, since the data changes from “H” to “L” within the data setup time tsu=1.5(ns), it is not possible to correctly carry out the data sampling.
In contrast, in FIG.
20
(
b
), at the time that is 3(ns) to the rising of the clock signal, the 1 bit of the data falls down to “L” from “H”. In this case, since the data changes from “H” to “L” prior to reaching the data setup time tsu=1.5(ns), the sampling is made to the “L” of the data.
As is clear from the foregoing description, when the sampling is carried out with respect to the data in synchronization with the rising of the clock signal, the time period in which the data can be changed, i.e., the data sampling margin is indicated by the oblique line shown in FIG.
21
. Namely, the data sampling margin corresponds to the period between the time when time th (the data hold time th) is elapsed after the rising of the clock signal and the time that is tsu (the data setup time) to the rising of the next clock signal.
For example, when it is assumed that the duty ratio of the clock signal is 50 percent, since the clock period Tck is equal to 25(ns), the data sampling margin is 22.5(ns)(=Tck−tsu−th=25(ns)−1.5(ns)−1(ns)) in the case of SVGA. The data sampling margin is 12.88(ns)(=Tck−tsu−th=15.38(ns)−1.5(ns)−1(ns)) in the case of XGA because the clock period Tck is equal to 15.38(ns).
Further, in actual, it takes more time for the clock signal and the data signal to rise up or fall down and it is necessary to consider the time required for the data signal to fall down to a threshold voltage (for example, 0.3×VCC) so as to be recognized to be “L” or the data signal to rise up to a threshold voltage (for example, 0.7×VCC) so as to be recognized to be “H”. This results in that the time differences A and B when the time required for the above-mentioned rising and falling is not considered becomes longer the time differences A′ and B
Conlin David G.
Daley, Jr. William J.
Edwards & Angell LLP
Hjerpe Richard
Nguyen Kimnhung
LandOfFree
Signal transfer system, signal transfer apparatus, display... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal transfer system, signal transfer apparatus, display..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal transfer system, signal transfer apparatus, display... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3295238