Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-02-15
2003-11-11
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S082000, C326S083000, C326S093000
Reexamination Certificate
active
06646471
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal transfer circuit provided between one transmission side circuit for transmitting a digital signal and one or more reception side circuit for receiving the digital signal.
In the prior art, a digital signal is transferred between ICs typically by using a voltage signal at a low level (e.g., a GND voltage) and a voltage signal at a high level (e.g., a Vdd voltage).
FIG. 8
is an electric circuit diagram illustrating a configuration of a conventional signal transfer circuit using CMIS devices. As illustrated in the figure, the transmission side IC includes an output circuit
110
(inverter) between a terminal for supplying a power supply voltage (Vdd) and the ground. The output circuit
110
includes a first p-channel transistor
102
and a first n-channel transistor
101
connected in series with each other. The reception side IC includes an input circuit
111
(inverter) between a terminal for supplying a power supply voltage (Vdd) and the ground. The input circuit
111
includes a second p-channel transistor
104
and a second n-channel transistor
103
connected in series with each other. An external terminal
105
of the transmission side IC and an external terminal
106
of the reception side IC are connected to each other via a signal transfer path
107
. Thus, a digital signal can be transferred between the transmission side IC and the reception side IC.
In the transmission side IC, as a digital signal Sdg is input from an internal circuit to the gate of each of the transistors
101
and
102
of the output circuit
110
, a low-level signal is output from the output circuit
110
if the digital signal Sdg is at the high level and a high-level signal is output from the output circuit
110
if the digital signal Sdg is at the low level. Then, as the digital signal is input to the input circuit
111
of the reception side IC via the external terminals
105
and
106
, the digital signal is output to an internal circuit of the reception side IC while being inverted again by the input circuit
111
.
In recent years, however, the signal transfer speed has been increasing and the number of signals transferred has also been increasing. Accordingly, the electromagnetic interference (EMI) has become problematic in the conventional circuit as described above.
When the level of the signal output from the output circuit
110
is switched from the low level to the high level, or vice versa, a large current flows along the signal transfer path
107
according to the potential transition.
The current occurring due to such potential changes increases as the change in voltage along the signal transfer path
107
is greater. Therefore, the amount of fluctuation of the current value increases as the operating speed of the transistors provided in the output circuit or the input circuit increases. As a result, electromagnetic waves occur along the signal transfer path
107
, and the electromagnetic interference caused by the electromagnetic waves may adversely affect the peripheral devices.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a signal transfer circuit with little electromagnetic interference along a signal transfer path by employing means for suppressing the change in voltage along the signal transfer path.
A signal transfer circuit of the present invention is a signal transfer circuit for connecting one transmission side circuit and one or more reception side circuit via a signal transfer path including one signal transfer line per signal, the signal transfer circuit including: an output transistor, provided between one voltage supply section in the transmission side circuit and the signal transfer path, for operating according to a digital signal from an internal circuit of the transmission side circuit; a node, located in the reception side circuit and connected to an internal circuit of the reception side circuit, for outputting a digital signal to the internal circuit of the reception side circuit; a reception transistor located in the reception side circuit between the node and the signal transfer path; and precharge means for precharging the node so as to cause a potential difference between the voltage supply section of the transmission side circuit and the node.
In this way, the output transistor of the transmission side circuit is either allowing a current to flow from the signal transfer path to one voltage supply section or in an open state. When the current flows, the potential of the signal transfer path is substantially equal to the voltage of the one voltage supply section. When in the open state, the potential of the signal transfer path is determined by the voltage supplied from the reception transistor of the reception side circuit. Therefore, by producing, in the reception side circuit, a digital signal to be supplied to the internal circuit by utilizing the change in the potential difference between the node and the one voltage supply section, it is possible to output a digital signal having a sufficient logic amplitude to the internal circuit of the reception side circuit even if the voltage amplitude of the signal transfer path is lowered to about several hundred mV, for example. Therefore, the electromagnetic interference (EMI) can be significantly reduced as compared to a case where a digital signal having a large voltage amplitude that transitions between the high level and the low level is transferred along the signal transfer path as in the prior art.
Moreover, with the clock frequency being equal, the signal transfer speed can be doubled for a signal transfer circuit that requires two signal lines per signal.
It is preferred that the precharge means operates according to a mode switching signal that is synchronized with a clock signal.
The signal transfer circuit may further include latch means for supplying the digital signal output from the node of the reception side circuit to the internal circuit of the reception side circuit in synchronism with the clock signal. In this way, it is possible to reliably send the digital signal into the internal circuit of the reception side circuit.
The signal transfer circuit may further include switching means for receiving a first voltage signal and a second voltage signal having different potentials from each other and alternately supplying the first voltage signal and the second voltage signal to the reception transistor according to the mode switching signal. In this way, it is possible to smoothly control the signal transfer operation.
The signal transfer circuit may employ a configuration in which: the precharge means is a MIS transistor whose source is connected to a power supply voltage supply section, whose gate receives the mode switching signal and whose drain is connected to the node; the reception transistor is a MIS transistor whose source is connected to the signal transfer path and whose drain is connected to the node; and the switching means is a selector circuit for alternately supplying the first voltage signal and the second voltage signal to the gate of the reception transistor according to the mode switching signal. In this way, the signal transfer circuit has a circuit configuration suitable for a case where MIS type semiconductor devices are used.
The signal transfer circuit may further include a level adjustment transistor, provided between the precharge transistor and the node, for adjusting the voltage level of the node. In this way, it is possible to prevent a large voltage, due to a gate-drain coupling capacitance, from being applied to the node, in a case where the precharge transistor is a MIS transistor.
The signal transfer circuit may further include: a second node, located in a second reception side circuit and connected to the internal circuit of the second reception side circuit, for outputting a digital signal to the internal circuit of the second reception side circuit; a second reception transistor located in the second reception side circuit between the second node and the signal
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Tran Anh
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