Signal timing for I/O

Details Signal timing for I/O Signal timing for I/O

2005-12-15

2008-01-08

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189020, C365S233100

Reexamination Certificate

active

07317644

ABSTRACT:
Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output write timing so the output can achieve better performance, such as higher maximum frequency of output (Fmax) performance. The delay cells ensure that critical timing criteria between clock signals and data high and low signals are satisfied so that there is a reduced chance of output glitching.

REFERENCES:
patent: 6614371 (2003-09-01), Zhang
patent: 6646944 (2003-11-01), Shimano et al.
patent: 6735129 (2004-05-01), Akasaki et al.
patent: 7026850 (2006-04-01), Atyunin et al.
patent: 2005/0034006 (2005-02-01), Schoenfeld et al.

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