Signal timing adjustment device, signal timing adjustment...

Details Signal timing adjustment device, signal timing adjustment... Signal timing adjustment device, signal timing adjustment...

2004-03-26

2008-11-04

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000, C375S355000, C375S356000, C375S357000, C375S358000, C327S158000, C327S146000, C327S149000, C327S153000, C327S161000

Reexamination Certificate

active

07447289

ABSTRACT:
Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

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Deleganes et al., 2002 Symposium on VLSI Circuits Digest of Technical Papers, 4 pages.

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