Signal termination scheme for high speed memory modules

Details Signal termination scheme for high speed memory modules Signal termination scheme for high speed memory modules

2009-05-21

2010-11-30

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S033000

Reexamination Certificate

active

07843213

ABSTRACT:
A memory device is coupled to a subset of lines of a data input/output (I/O) bus. The memory device includes an on-die active termination circuit for terminating the subset of lines of the data I/O bus with a selected impedance being one of a plurality of selectable impedances; a termination value register being coupled to the on-die active termination circuit for storing a value representing the selected impedance; and a termination value setting circuit being coupled to the termination value register, for setting the value representing the selected impedance in the termination value register.

REFERENCES:
patent: 6356106 (2002-03-01), Greeff et al.
patent: 2003/0126338 (2003-07-01), Dodd et al.
patent: 2010/0030934 (2010-02-01), Bruennert et al.

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