Signal storing circuit semiconductor device, gate array and...

Details Signal storing circuit semiconductor device, gate array and... Signal storing circuit semiconductor device, gate array and...

1999-11-05

2001-05-15

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

Reexamination Certificate

active

06233169

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
All the contents disclosed in Japanese Patent Application No. H10-315806 (filed on Nov. 6, 1998), including specification, claims, drawings and abstract and summary is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to signal storing circuits and devices related thereto, more specifically to the signal storing circuits and devices related thereto using ferroelectrics.
2. Description of the Related Art
IC-cards are used for credit cards and for identification tags in distributing systems. Recently, IC-cards mounting logic LSIs (large scale integrated circuit) thereon as well as installing micro-computers therein are commercially available. A circuit shown in
FIG. 26
is known as a sequence logic processing circuit used for the logic LSIs and the microcomputers.
The logic processing circuit
2
shown in
FIG. 26
comprises a combined logic block CB including NAND circuits and/or OR circuits and a latching block LT latching an output of the combined logic block CB. The combined logic block CB performs a predetermined logic operation to an input data IN provided thereto, and outputs a resulting data OUT therefrom. The latching block LT latches the resulting data OUT at the positive edge (Low-to-high transition) or the negative edge (High-to-low transition) of a clock pulse Cp. The data OUT thus latched therein is outputted as an output data Q.
With the logic processing circuit
2
, the data OUT latched can be outputted within a duration equivalent to a time period in which upcoming clock pulse Cp is detected by latching the data OUT at the positive edge (or negative edge) of the clock pulse Cp. In this way, a stable output can be obtained by eliminating noises from the resulting data.
Sequential processing having a high reliability and other related using a combination of a plurality of the logic processing circuits
2
can perform processing.
The conventional processing circuit
2
described above, however, has the following problems to be solved. An adequate voltage must be applied to the circuit
2
all the time in order to hold the data being processed.
Data being processed under sequential processing and that stored in a memory are completely erased when the power supply is shut off by an accident. The data can not be recovered even after the recovery of the power supply. In order to recover the data into the original one just before the accident, another sequential processing must be performed all over again from its beginning. It consumes much time to perform the sequential processing for every accident, and the data erase cause serious damages on the reliability in processing.
The power supply would be in unstablized when the circuit is used for a non-contact type IC card because the power is supplied thereto through radio waves. Suspension in the power supply makes the processing difficult especially when a greater amount of data need to be processed under the real-time basis.
In order to suppress the power consumption of the circuit, a low-power consumption type-latching block LT shown in
FIG. 27
is proposed. This is achieved by utilizing transistor(s) having a high threshold voltage, which lower the power consumption.
A circuit
4
having a low threshold voltage comprises inverter circuits INV
0
and INV
1
both including low threshold transistors, which can operate fast in operating speed but consume much power. A circuit
6
having a high threshold voltage, on the contrary, comprises inverter circuits inverter circuits INV
2
and INV
3
both including high threshold transistors which are operated slowly in operating speed but consume not much power.
A power control part
8
supplies the power to the circuit
4
when the circuit
2
is in operation, and the control part
8
suspends the power supply to the circuit
4
when the circuit
2
is in stand-by State. In this way, the resulting data OUT is outputted through the inverter circuits INV
0
and INV
1
both can operate fast in operating speed during the operating-State, and the data OUT is stored in the inverter circuits INV
2
and INV
3
both consumes not much power during the stand-by State. It is, therefore, preferred for the circuit
2
to store the data OUT in such a way.
Although, the low-power consumption type-latching block LT shown in
FIG. 27
during the Stand-by State consumes a relatively smaller power, it still consumes the power.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the above mentioned problems on a prior art logic processing circuit and to provide signal storing circuits and related devices capable of storing resulting data even when the power supply thereto is suspended, and to provide the signal storing circuit which consumes less power.
In accordance with characteristics of the present invention, there is provided a signal storing circuit storing a signal therein for a predetermined time period, the circuit comprises:
a signal path for passing the signal therethrough; and
a ferroelectric memorizing portion connected to the signal path and holding a polarization-State corresponding to a signal on the signal path in an operating-State even after shut off the circuit while reproducing the signal on the signal path in accordance with the polarization-State thus held therein when the circuit is again in operation.
A word “ferroelectric memorizing portion” used in claims represents a portion, which stores data, by using hysteresis of ferroelectrics. In a concrete form, the ferroelectric memorizing portion includes a ferroelectric transistor and a ferroelectric capacitor, not only those, a circuit or equivalents combining these may be included. An inverter circuit INV
2
shown in
FIG. 1
forms the memorizing portion.
Further, another words “a ferroelectric transistor” used in claims represents a transistor using ferroelectrics such as a transistor having a structure so called MFMIS and an MFS-structured transistor both of which will be described subsequently. In the preferred embodiments, transistors NT and PT shown in
FIG. 4
form the ferroelectric transistor.
While the novel features of the invention are set forth in a general fashion, both as to organization and content, along with other objects and features thereof from the following detailed description taken in conjunction with the drawings.


REFERENCES:
patent: 5603043 (1997-02-01), Taylor et al.
patent: 5896042 (1999-04-01), Nishimura et al.
patent: 5905671 (1999-05-01), DeVilbiss
patent: 5949706 (1999-09-01), Chang et al.

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