Signal selecting device controlled by a serially transmitted mod

Details Signal selecting device controlled by a serially transmitted mod Signal selecting device controlled by a serially transmitted mod

1994-08-31

1996-04-30

Heyman, John S.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

34082568, 377 56, 377 76, 377 54, H03K 1700, H03K 3027

Patent

active

055128467

ABSTRACT:
In a signal selecting device, a mode determination portion 61 comprises a shift register 11, a clock generating portion 20 and decoder 51. The clock generating portion 20 receives a mode signal M and generates a clock signal CK1 used for decoding the mode signal M from a system clock SYS. The shift register 11 receives the mode signal M and the clock signal CK1 and outputs signals Q.sub.0 to Q.sub.3. The decoder 51 receives the output from the shift register 11 and outputs control signals S.sub.00 to S.sub.03. Therefore, there needs only one terminal for receiving the mode signal M and no terminal for receiving a clock.

REFERENCES:
patent: 3633166 (1972-01-01), Picard
patent: 3774056 (1973-11-01), Sample et al.
patent: 3849634 (1974-11-01), Saltini et al.
patent: 4127823 (1978-11-01), Frost
patent: 4935944 (1990-06-01), Everett
patent: 5060244 (1991-10-01), Robertson
patent: 5323438 (1994-06-01), Kim
Halbleiter-Schaltungstechnik, Tietze, et al., 1983, 6th editon, pp. 224-227 .

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