Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Patent
1995-09-14
1997-04-22
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
257513, 257661, 257529, 257530, 257665, 257 50, 257709, 257774, 257758, 257700, 505220, H01L 2348, H05K 114, H05K 105
Patent
active
056231601
ABSTRACT:
Method and apparatus for interconnecting integrated circuits (ICs) are described. The invented lattice preferably is formed in a plural-layer structure whereby each required interconnect signal has one or more dedicated layers of a planar, thin-film conductor that is coextensive with the substrate. Thousands of such horizontal layers are vertically stacked in the structure, each being shielded by voltage or ground planes and each being insulated by layers of insulative dielectric material. A regular array of vertical pillars is provided in the substrate, each pillar effectively providing an inner conductor either electrically connected with a conductive layer or electrically insulated therefrom by an insulative region. The columns extend from the top of the substrate on which the ICs are mounted through to the bottom surface of the bottom layer. The pillars may be selectively disconnected from the layers by fusing techniques, or, alternatively, the pillars may be selectively connected to the layers by anti-fusing techniques. In one embodiment, the interconnection region between a pillar and a layer is switchably programmable to either interconnect or disconnect via a semiconductor switching device such as a transistor fabricated in the lattice interconnect structure, whereby each pillar's interface with each layer may be selectively and alterably defined as being conductive or insulative. Preferably, each column includes a bonding pad on the upper structure surface for surface mounting or wire bonding of selected I/O contacts of the ICs. Voltage and ground planes may be rendered in the same substrate by a technique involving the fusing or anti-fusing of selected vias so that they are electrically connected with a given plane representing a voltage or ground potential. Such also may be performed by forming vias and selectively plating them through, as by photolithographic techniques, to produce the desired connections.
REFERENCES:
patent: 4353040 (1982-10-01), Krumm et al.
patent: 4450029 (1984-05-01), Holbert et al.
patent: 4457803 (1984-07-01), Takigawa
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4498122 (1985-02-01), Rainal
patent: 4598166 (1986-07-01), Neese
patent: 4698129 (1987-10-01), Puretz et al.
patent: 4796269 (1989-01-01), DeFreeze et al.
patent: 4797892 (1989-01-01), DeFreeze et al.
patent: 4827327 (1989-05-01), Miyanchi et al.
patent: 4888665 (1989-12-01), Smith
patent: 4899439 (1990-02-01), Potter et al.
patent: 5057877 (1991-10-01), Briley et al.
patent: 5061824 (1991-10-01), Alexander et al.
patent: 5136471 (1992-08-01), Inasaka
patent: 5137836 (1992-08-01), Lam
patent: 5216806 (1993-06-01), Lam
patent: 5222014 (1993-06-01), Lin
patent: 5241450 (1993-08-01), Bernhardt et al.
patent: 5247423 (1993-09-01), Lin et al.
patent: 5264664 (1993-11-01), McAllister et al.
patent: 5264729 (1993-11-01), Rostoker et al.
patent: 5306670 (1994-04-01), Mowatt et al.
patent: 5309024 (1994-05-01), Hirano
patent: 5314840 (1994-05-01), Schepis et al.
patent: 5319238 (1994-06-01), Gordon et al.
patent: 5325268 (1994-06-01), Nachnani et al.
patent: 5327327 (1994-07-01), Frew et al.
patent: 5329157 (1994-07-01), Rosotker
patent: 5341092 (1994-08-01), El-Ayat et al.
patent: 5349248 (1994-09-01), Parlour et al.
patent: 5359493 (1994-10-01), Chiu
patent: 5373109 (1994-12-01), Argyrakis et al.
patent: 5408130 (1995-04-01), Woo et al.
patent: 5475264 (1995-12-01), Sudo et al.
SiC Film Deposited by Pulse Laser Ablation, Mat. Res. Soc. Symp., vol. 191, p. 61 (1990) (copy not enclosed).
L. Rimai et al., Deposition of Thin Films of Silicon Carbide on Fused Quartz and on Sapphire by Laser Ablation of Ceramic Silicon Carbide Targets, Mat. Res. Soc. Symp., vol. 285, p. 495 (1993) (copy not enclosed).
M.A. El Khakani et al., Deposition of Silicon Carbide Thin Films by Pulsed Excimer Laser Ablation Technique in the (25-700).degree.C Deposition Temperature Range, Proc. SPIE, vol. 2403 (1995) (copy not enclosed).
Integral Decoupling Capacitance Reduces Multichip Module Ground Bounce, Todd Takken, Dept. of Electrical Engineering, Stanford, 1993, IEEE, pp. 79-84.
An Overview of Multichip Modules, Predeep Lall et al., Advanced Device Packaging, Sep., 1993, Solid State Technology, pp. 65-72.
Laser Ablation and Laser Etching, J. Boulmet et al., Institut d'Electronique Fondamentale, Paris, France.
Comparison of the Ablation of Dielectrics and Metals at High and Low Laser Powers, R. W. Dreyfus, IBM Research Division, New York.
Crane Sara W.
Williams Alexander Oscar
LandOfFree
Signal-routing or interconnect substrate, structure and apparatu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal-routing or interconnect substrate, structure and apparatu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal-routing or interconnect substrate, structure and apparatu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-343486