Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1997-02-27
1999-03-09
Tokar, Michael
Electronic digital logic circuitry
Interface
Logic level shifting
326 73, 326 71, H03K 19094
Patent
active
058806016
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a signal receiving circuit and to a digital signal processing system and, particularly, to technology that can be effectively utilized for transferring signals between semiconductor integrated circuit devices having different operation voltages and different types of internal logic circuits.
BACKGROUND ART
In some digital integrated circuits, small signals such as of the ECL level are transmitted based upon a power source voltage VCC such as GTL (gunning transceiver logic) or +5 V in order to transmit signals at high speeds over a signal transmission line and to decrease the consumption of electric power. The GTL has been disclosed in ISSCC, International Solid State Circuit Conference, Feb. 19, 1992, pp. 58-59.
DISCLOSURE OF THE INVENTION
As described above, there are various kinds of low-amplitude interfaces having their own features. Therefore, they will never be uniformalized into a single kind of low-amplitude interface but rather it is quite probable that new amplitude interfaces will be developed in the future. Under such circumstances where there exist various kinds of low-amplitude interfaces being mixed together, it becomes necessary to design receiving circuits of semiconductor integrated circuit devices to meet the interfaces. The present inventors therefore have devised a signal receiving circuit that can be adapted to various kinds of low-amplitude interfaces to constitute an optimum system which includes semiconductor integrated circuit devices having various interfaces in a mixed manner.
The object of the present invention therefore is to provide a signal receiving circuit capable of being adapted to various kinds of low-amplitude interfaces as well as to provide a novel digital signal processing system which permits the inclusion of various kinds of low-amplitude interfaces.
The above-mentioned and other objects as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.
Among the inventions disclosed in this application, a representative example will now be briefly described below. That is, the invention employs a first P-channel MOSFET amplifier and a first N-channel MOSFET amplifier having gates supplied with positive signals from a pair of signal transmission lines, and a second P-channel MOSFET amplifier and a second N-channel MOSFET amplifier having gates supplied with negative signals from said pair of signal transmission lines, and forms a first output signal is formed by so adjusting the gains of the first P-channel MOSFET amplifier and of the second N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages, and forms a second output signal by so adjusting the gains of the second P-channel MOSFET amplifier and of the first N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages, making it possible to receive various small signals lying over a wide range even by using a sense amplifier which has only a fixed operation range based upon the level-shifting actions of only said two MOSFET amplifiers and load MOSFETs.
Moreover, complementary digital output signals having different levels are sent onto a pair of first and second signal transmission lines and are received by a first (second) receiving circuit which comprises a first (third) P-channel MOSFET amplifier and a first (third) N-channel MOSFET amplifier having gates supplied with positive signals; a second (fourth) P-channel MOSFET amplifier and a second (fourth) N-channel MOSFET amplifier having gate supplied with negative signals, said first (second) receiving circuit forming a first (third) output signal by so adjusting the gains of the first (third) P-channel MOSFET amplifier and of the second (fourth) N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages and forming a second (fourth) output signal by so adjust
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Ito Kunihiro
Kanazawa Nobuaki
Mizukami Masao
Hitachi , Ltd.
Hitachi Communication Systems, Inc.
Roseen Richard
Tokar Michael
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