Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-04
2001-07-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C340S870030
Reexamination Certificate
active
06263481
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reprogrammable combinational circuit wherein an optimization of the signal running time may be realized after the circuit is already programmed.
2. Description of the Prior Art
A commercially available, reprogrammable combinational circuit is typically programmed with a code (bit stream) that determines which individual circuit in the combinational circuit to be programmed. Thus, a nearly arbitrarily prescribable circuit can be programmed into the reprogrammable combinational circuit.
The reprogrammable combinational circuit includes a plurality of cells, wherein each cell contains a combinational block and a register. The combinational blocks, in turn, perform operations corresponding to a prescribable circuit wherein the registers can be switched between a “used” and “unused” state. Accordingly, the registers allow the circuit to become a synchronous circuit, equivalent to a synchronous combinational circuit, dependent on a clock signal.
A person skilled in the art knows that synchronous circuits are those that are based on a common clock and that switch at identical points in time; whether at the positive edge or the negative edge of the clock signal. A definition of synchronous combinational circuit (=synchronous circuit) is provided in H. -J. Schneider,
Lexikon der Informatik und Datenverarbeitung
, 2
nd
Edition, Oldenbourg Verlag, Munich 1986, ISBN 3-486-22662-2, pp. 508, 509.
Combinational blocks lie between registers in the development of synchronous circuits. The signal running time through the combinational blocks as well as setup time and hold time of the registers determine the maximum clock frequency with which the synchronous circuit can be operated.
The maximum clock frequency of a reprogrammable combinational circuit is often inadequate in practice. An enhancement of such performance capability, therefore, would be desirable.
SUMMARY OF THE INVENTION
The present invention is directed toward optimizing the signal running time in a reprogrammable combinational circuit, wherein the optimization is implemented after the programming of the reprogrammable combinational circuit.
This object is achieved in a method wherein the reprogrammable combinational circuit is programmed with the prescribable circuit. A row of combinational blocks and registers is thereby formed such that each register is optionally connected either used or unused. The optimization of the signal running times occurs after the programming in that pluralities of combinational blocks respectively between two registers switched used are selected approximately equal in the row.
The present invention also teaches a reprogrammable combinational circuit that contains a program code optimized in signal running time, wherein approximately equal pluralities of combinational blocks are arranged between registers switched used. It is advantageous to implement the optimization of the signal running times after the programming of the combinational circuit since the signal running times can be exactly identified at this time. As such, the optimization is not based on a mere estimate.
Additional features and advantages of the present invention are described in, and will be apparent from, the Detailed Description of the Preferred Embodiments and from the Drawings.
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CIP-Kurztitelaufnahme der Deutschen Bibliothek.
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
Smith Matthew
Spreight Jibreel
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