Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-11-01
2001-09-11
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S276000, C327S284000
Reexamination Certificate
active
06288578
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal processor for a charge coupled device, and more particularly to a signal processor for a charge coupled device, wherein the signal processor has a noise canceller circuit for canceling noises of the charge coupled device.
The charge coupled device has been decreasing in size and has been improved to realize multiple pixels. Almost 100% of the image pick-up devices for television cameras are charge coupled devices. Diffusion and improvement in characteristics of electronic still camera have rendered development of the charge coupled device for the electronic still camera with one million pixels. The developments for the electronic still camera have focused on the multiple pixels and size reduction. The development to the electronic still camera for realizing the multiple pixels has caused a size reduction in each pixel. This reduction in size of the multiple pixel causes a problem with a reduction in quantity of signal charge. This reduction in quantity of signal charge causes reductions in sensitivity and dynamic range. In order to obtain sufficiently high sensitivity and dynamic range, a further noise reduction of the charge coupled device is essential, For realizing the noise reduction of the charge coupled device, various types of noise cancellation circuits have been proposed. One type of the noise cancellation circuits is a reflective delay-difference noise cancellation circuit is disclosed in Japanese patent No. 2522068, Japanese laid-open patent publication No. 1-208975, Japanese laid-open patent publication No. 3-80679, Japanese laid-open patent publication No. 4-43775, and Japanese laid-open patent publication No. 4-339477, wherein a difference between a field through level and an effective signal level is found by utilizing the reflection on a delay line so as to extract the effective signal via a switching circuit. This reflective delay-difference noise cancellation circuit is advantageous in relatively stable high speed performance and less returning of a high frequency band noise to a low frequency band noise. This circuit configuration is most effective for suppression of the noise.
FIG. 1
is a circuit diagram illustrative of the conventional reflective delay-difference noise cancellation circuit disclosed in Japanese patent No. 2522068.
The first noise cancellation circuit has a first buffer circuit
2
which has an input terminal connected to an output terminal of a charge coupled device image pick-up device
1
. The first noise cancellation circuit has a first resistance
11
which is connected to an output side of the first buffer
2
. The first noise cancellation circuit also has a second buffer circuit
7
which has an input terminal connected through the first resistance to the output terminal of the first buffer
2
. The first noise cancellation circuit also has a delay line
13
which is connected between a ground line and a first node N
1
between the first resistance
11
and the second buffer circuit
7
. The first noise cancellation circuit also has a second resistance
12
which is connected to an output terminal of the second buffer circuit
7
. The first noise cancellation circuit also has a first switch
9
which is connected through the second resistance
12
to the output terminal of the second buffer circuit
7
. The first switch
9
is also connected between the second resistance and a second node N
2
. The first noise cancellation circuit also has a first capacitance
10
which is connected between the second node N
2
and the ground line. The first resistance
11
has the same resistance as a specific impedance of the delay line
13
. The delay line
13
has an output terminal which is grounded. An output signal from the charge coupled device image pick-up device
1
is transmitted through the first buffer circuit
2
and the first resistance
11
to the delay line
13
. The signal is further transmitted from the delay line
13
to the second buffer circuit
7
and the second resistance
12
to the first switch
9
which is connected to the capacitance
10
as a hold capacitor.
FIG. 2
is a diagram illustrative of a time chart for operations of the first conventional circuit of FIG.
1
. The output signal waveform is cyclic. One cycle for each pixel of the output signal from the charge coupled device may be classified or divided into three time periods. The first time period is a reset time period (a). The second time period is a field through time period (b). The third time period is a signal time period (c). An effective signal voltage level for one pixel appears to be potential differences Vs
1
, Vs
2
and Vs
3
between the field through time period (b) and the signal time period (c). The output signal (A) from the first buffer circuit
2
is transmitted through the first resistance
11
to the delay line
13
, wherein the output signal (A) reaches the grounded output terminal with a time delay &tgr; and inverted and reflected at the grounded output terminal, and then the delay signal reaches to the input terminal with the time delay &tgr;. A total delay time of the delayed signal (B) is 2 &tgr;. This total delay time 2 &tgr; is set so that the signal time period of the output signal (A) is superimposed over the field through time period of the delayed signal (B),
10
whereby the output signal (A) transmitted through the first resistance
11
is mixed at the input terminal of the delay line
13
with the delayed signal (B) transmitted through the delay line
13
. The mixture of the output signal (A) with the delayed signal (B) makes an output signal (C). The output signal (C) is then transmitted through the second buffer circuit
7
and the second resistance
12
. For the output signal (C), the effective signal voltage is subjected to amplification-modulation and is represented to be the potential differences Vs
1
′, Vs
2
′ and Vs
3
′.
A sample pulse signal (D) is applied to the switch circuit
9
so that only the effective signal voltage Vs
1
′, Vs
2
′ and Vs
3
′ pass through the switch
9
. The foregoing processes provides that the effective signal voltage which corresponds to the potential difference between the field through time period and the signal time period is subjected to a sampling with elimination of a noise component which has been superimposed in the field through time period and the signal time period.
FIG. 3
is a block diagram illustrative of a noise cancellation circuit for the charge coupled device disclosed in Japanese laid-open patent publication No. 4-43775. The second noise cancellation circuit has a level shift resistor
102
which is connected to an image pick-up region
101
. The second noise cancellation circuit also has an output circuit
103
which is connected to the level shift resistor
102
. The second noise cancellation circuit also has a buffer circuit
104
which is connected to an output terminal of the output circuit
103
. The second noise cancellation circuit also has a resistance
105
which is connected to an output terminal of the buffer circuit
104
. The resistance
105
is thus connected between the output terminal of the buffer circuit
104
and a node N
1
. The second noise cancellation circuit also has a delay line
108
which is connected to the node N
1
and also connected to a ground line. The second noise cancellation circuit also has a switch
109
which has a first terminal connected to the output side of the delay line
108
, a second terminal connected directly to the ground line and a third terminal connected through a resistance
111
to the ground line. The switching operation of the switch
109
selects one of first and second states. In the first state, the first terminal and the second terminal are connected to each other so that the output signal from the delay line
108
is transmitted through the switch
109
to the ground line the output from the delay line
108
to be transmitted to the ground line or transmitted through the switch
109
. In the second state, the
Callahan Timothy P.
Luu An T.
NEC Corporation
Young & Thompson
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