Signal processing system for reducing power consumption

Details Signal processing system for reducing power consumption Signal processing system for reducing power consumption

2004-01-28

2009-06-02

Phan, Raymond N (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S106000, C713S323000

Reexamination Certificate

active

07543092

ABSTRACT:
A system for data communication purposes in electronic devices comprises a data bus comprising first, second, third and forth signal paths. A first control means generates a first state of a control signal in the presence of a clock signal in a first mode of operation. The first operation mode may be the normal operation mode of a consumer electronic apparatus. A second control means generates a second state of the control signal in the presence of a clock signal in a second mode of operation. The second operation mode may be the stand-by mode of the consumer electronic apparatus. The system can be easily integrated into existing systems utilizing e.g. a VFD protocol.

REFERENCES:
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patent: 5664124 (1997-09-01), Katz et al.
patent: 5852406 (1998-12-01), Edde et al.
patent: 6002882 (1999-12-01), Garde
patent: 6457078 (2002-09-01), Magro et al.
patent: 2001/0005874 (2001-06-01), Domon
US 5,909,590, 06/1999, Garde (withdrawn)
Search Report dated Jul. 9, 2004.

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