Signal processing device having PLL circuits

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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331 25, H03D 324, H03L 700

Patent

active

056663870

ABSTRACT:
A signal processing device includes a first PLL circuit operating in synchronism with a serial input data signal, and a second PLL circuit operating in synchronism with an external reference clock signal. The oscillation frequency of the first PLL circuit is controlled by the second PLL circuit.

REFERENCES:
patent: 4336508 (1982-06-01), Cole et al.
patent: 4496977 (1985-01-01), Ikeda
patent: 4633193 (1986-12-01), Scordo
patent: 5072195 (1991-12-01), Graham et al.
patent: 5319680 (1994-06-01), Port et al.
European Search Report dated May 18, 1995.

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