Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1995-02-14
1995-12-26
Westin, Edward P.
Electronic digital logic circuitry
Interface
Logic level shifting
326 75, 326 77, H03K 190175
Patent
active
054791154
ABSTRACT:
There is disclosed a signal processing device which includes a pre-processing circuit (31) for performing a serial-to-parallel conversion on an intermediate signal (M.sub.2) at a PECL level, the serial-to-parallel conversion at the PECL level being permitted to deal with a high frequency, and a level converter circuit (12) for performing a conversion from the ECL to PECL levels both having the same logic level width, which conversion consumes less power than a conversion between the ECL and CMOS levels having different logic level widths. The level conversion of a parallel signal requires less power consumed than a level conversion of a serial signal. The signal processing device further includes a level converter circuit (13) for performing a conversion into the CMOS level after obtaining an intermediate signal (M.sub.3) which is a parallel signal. An intermediate signal (M.sub.4) is at the CMOS level and has a low frequency. The signal processing device which operates at the CMOS level processes the high-frequency signal at the ECL level for reduction in consumed power.
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National Semiconductor Corporation Product Catalog, Dec. 1990, "NGM Series ABiC BiCMOS/ECL Gate Arrays", pp. 1-11.
NEC Technical Report, vol. 43, No. 12, 1990, "BiCMOS Gate Arrays", Tsutomu Hatano, pp. 119-121 (with partial English translation).
Hayakawa Yasushi
Ueda Masahiro
Mitsubishi Denki & Kabushiki Kaisha
Sanders Andrew
Westin Edward P.
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