Signal processing delay circuit

Details Signal processing delay circuit Signal processing delay circuit

1995-04-25

1997-06-03

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, 331 17, H04L 700

Patent

active

056362544

ABSTRACT:
A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.

REFERENCES:
patent: 5036297 (1991-07-01), Nakamura
patent: 5119045 (1992-06-01), Sato
patent: 5295164 (1994-03-01), Yamamura
patent: 5404250 (1995-04-01), Hose et al.

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