Signal processing circuit with timing recovery PLL

Details Signal processing circuit with timing recovery PLL Signal processing circuit with timing recovery PLL

1999-10-29

2003-11-04

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error detection for synchronization control

C714S700000

Reexamination Certificate

active

06643820

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a signal processing circuit, and more particularly, to a signal processing circuit including a timing recovery PLL for matching a clock signal with preamble data signal read from a recording medium and a decision feedback equalizer for reproducing code data recorded on the recording medium based on the clock signal, and to a method for controlling the signal processing circuit.
A decision feedback equalizer (DFE) reproduces data read from a recording medium in accordance with a clock signal generated by a timing recovery PLL. The timing recovery PLL performs a so-called matching operation, in which the output timing of the clock signal is matched with the output timing of the reproduction data from the DFE based on preamble data (matching pattern) recorded on the recording medium.
FIG. 1
is a schematic block diagram showing a prior art signal processing circuit. The signal processing circuit
10
includes an analog-to-digital converter (ADC)
11
, a DFE
12
, two coefficient registers
13
,
14
, a PLL phase error detection circuit
15
, a timing recovery PLL (TR-PLL)
16
, and a control circuit
17
.
The ADC
11
samples the analog signal read from the recording medium in accordance with a clock signal CLK generated by the TR-PLL
16
and converts the analog data signal to a digital data signal. The digital data signal is sent to the DFE
12
.
The DFE
12
includes a forward (FW) filter
21
, an adder
22
, a comparator
23
, a shift register
24
, a feedback (FB) filter
25
, an inverter
26
, and three switches
27
,
28
,
29
.
The FW filter
21
is connected to the coefficent registers
13
,
14
via the first switch
27
. A first filter coefficient (start value) used by the FW filter
21
during start-up (i.e., during initiation of the reading operation) is stored in the first coefficient register
13
. A second filter coefficient (normal value) used by the FW filter
21
during normal operation (after detection of the preamble data) is stored in the second coefficient register
14
. Switching of the first switch
27
selectively sends the filter coefficient of the start value and the filter coefficient of the normal value to the FW filter
21
.
The FW filter
21
uses the first filter coefficient to filter the digital data signal from the ADC
11
in accordance with the clock signal CLK during the initial period of the reading operation to generate a signal S
1
having a maximum S/N ratio. The FW filter
21
uses the second filter value to perform filtering in the same manner during normal operation to generate the signal S
1
.
The adder
22
receives the filtered output signal S
1
from the FW filter
21
and a feedback signal S
2
from the FB filter
25
, and adds the output signal S
1
and the inverted signal of the feedback signal S
2
. In other words, the adder
22
functions as a subtractor, subtracting the feedback signal S
2
from the output signal S
1
.
The comparator
23
receives an added signal S
3
from the adder
22
, compares the voltage of the added signal S
3
with a reference voltage REF, and sends a determination signal S
4
, which is code data (i.e., one or zero) indicating the comparison result, to the shift register
24
via the second switch
28
.
The shift register
24
samples the determination signal S
4
from the comparator
23
in synchronism with the clock signal CLK and sequentially stores the sampled data. This stores the data, which comprises a plurality of bits, sampled in the past.
The data stored in the shift register
24
is output as a reproduction signal DATA. The data stored in the first bit of the shift register
24
(i.e., the determination signal S
4
) is the output as a reproduction signal DATA. In this manner, the DFE
12
reproduces code data recorded on the recording medium. The reproduction signal DATA is sent to an external apparatus, such as a microcomputer, after undergoing a data decoding process.
The FB filter
25
receives sampling data from the shift register
24
and eliminates interference between codes that is included in the sampling data. Further, the FB filter
25
outputs the feedback signal S
2
, which is based on the sampling data, having a plurality of bits and stored in the shift register
24
. The feedback signal S
2
is sent to the adder
22
via the third switch
29
.
The PLL phase error detection circuit
15
receives the added signal S
3
from the adder
22
and a signal S
6
, detects an error or difference between the phase of the read signal and the phase of the clock signal CLK based on the signals S
3
, S
6
, and generates a control signal S
7
in accordance with the detected error. The signal S
6
is either the determination signal S
4
of the comparator
23
or the output signal S
5
of the inverter
26
which are selected by the switching operation of the second switch
28
. The TR-PLL
16
receives the control signal S
7
from the PLL phase error detection circuit
15
, and matches the phase of the generated clock signal CLK with the phase of the read signal. The shift register
24
is used to perform sampling in accordance with the clock signal CLK from the TR-PLL
16
. The sampling is performed at the bit transmission speed of a read signal RD in order to store the determination signal in the shift register
24
. The detection signal corresponds to the recorded data on a magnetic disc,
The control circuit
17
receives the reproduction signal DATA from the shift register
24
and controls the switches
27
-
29
in accordance with the state of the reproduction signal DATA and the number of the bytes read subsequent to the initiation of the reading operation. The preamble data is data in which the pattern of a predetermined number of bits is repeated. A predetermined amount of preamble data is stored on the recording medium. Accordingly, the control circuit
17
controls the switches
27
-
29
at a predetermined timing based on the amount of preamble data read.
The control circuit
17
performs switch control as described below.
(1) When initiating the reading operation, the control circuit
17
moves the first switch
27
to the first coefficient register
13
, the second switch
28
to the comparator
23
, and opens the third switch
29
. Thus, the FW filter
21
uses the first filter coefficient (start value) from the first coefficient register
13
to shape the waveform of the digital signal from the ADC
11
. In this state, the adder
22
sends the output signal S
1
of the FW filter
21
to the comparator
23
since the third switch
29
is open. The error detection circuit
15
sends the control signal S
7
, which is based on the output signal S
1
(read signal) from the FW filter
21
, to the TR-PLL
16
. In this manner, the TR-PLL
16
performs phase matching in accordance with the read signal.
(2) When the control circuit
17
confirms from the reproduction signal DATA that the bit row showing the characteristics of the preamble data (in this case, “+++” or “−−−”) has been input a predetermined number of times (e.g., three times), the control circuit
17
moves the first switch
27
to the second coefficient register
14
, the second switch
28
to the inverter
26
, and closes the third switch
29
. Here, “+” indicates that the voltage of the sampled read signal RD is higher than the reference voltage REF, and “−” indicates that the voltage of the sampled read signal RD is lower than the reference voltage REF.
The FW filter
21
shapes the waveform of the digital signal from the ADC
11
using the second filter coefficient (normal value) from the second coefficient register
14
. The sampling data stored in the shift register
24
is inverted by the inverter
26
. The shift register
24
receives the inverted sampling data via the second switch
28
. Accordingly, the shift register
24
repetitively stores the bit row “+++−−−” of the preamble data. This initializes the sampling data in the shift register
24
to preamble data.
The adder
22
rec

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