Computer graphics processing and selective visual display system – Computer graphics processing – Attributes
Reexamination Certificate
1999-01-27
2002-04-16
Luu, Matthew (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Attributes
C345S582000, C345S589000, C345S606000, C345S605000, C345S600000
Reexamination Certificate
active
06373494
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processing apparatus which can perform a product summation operation at a high speed for, for example, linear interpolation, correction, etc. The present invention also relates to an image processing apparatus suitable for generating three-dimensional images in the field of computer graphics etc.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and amusement machines. In particular, systems using three-dimensional computer graphics have spread rapidly, along with the recent advances in image processing technology.
In three-dimensional computer graphics, one of the most widespread techniques used is the polygon rendering system. In such a system, a three-dimensional model is expressed as an composite of triangular unit graphics (polygons). The polygons are drawn, the colors of the pixels of the display screen are decided, and then the model is displayed on the display screen.
In such rendering processing, for example, when generating pixel data between the vertexes of the triangles or inside the triangles based on the vertexes, processing for linear interpolation is performed frequently at the time of giving highlighting to the texture data, at the time of texture mapping, and at the time of giving a fog effect.
The processing for linear interpolation performed in such a case can be expressed by the following formula 1:
A×&agr;+B×(1−&agr;) (1)
When performing the signal processing for linear interpolation as shown in formula 1, a configuration using two multipliers and one adder or a configuration using one multiplier, one subtractor, and one adder can be easily considered in an ordinary case.
Also, a configuration can be considered using the processor shown in FIG.
5
.
In the processor shown in
FIG. 5
, the operation [A×&agr;+B×(1−&agr;)] can be developed to the operation [A×&agr;+B×
−
&agr;+B] (where
−
&agr; indicates a bit inversion of &agr;) and evaluated by adding the adding term
B
and partial products out
—
0 to out
—
7 selected corresponding to the bits of the variable a to the values shifted as shown in FIG.
5
.
Note that the partial products out
—
0 to out
—
7 are values obtained for each bit of &agr; by selecting
A
when the bit is “1” and selecting
B
when the bit is “0”.
When performing the ordinary processing for linear interpolation as shown in formula 1 in an 8-bit processing system wherein, for example, the variables are 8-bit variables, if A=1, &agr;=1, and B=0 and performing normal multiplication, the operation shown in formula 2 is performed. When outputting the upper 8 bits as the result of the multiplication, the result is 0×FE.
0×FF×0×FF+0×(1−0×FF)=0×FE01 (2)
Note that FF indicates a hexadecimal number.
When mathematically considering 0 to 1.0 corresponding to 0×00 to 0×FF, 1.0×1≠1.0 is obtained, which means that the correct result of the operation can no longer be obtained.
Accordingly, for example, when applying this processing for linear interpolation to the fogging of the above three-dimensional computer graphics system, even when setting the fog coefficient to 1.0 so as not to give any fog effect at all, there is the problem that the input original pixel data is affected by something or another and the original pixel data cannot be maintained.
Therefore, up until now, use has been made of the result of the operation output from the processor shown in
FIG. 5
corrected when &agr;=1.0. With this, however, there is the problem that the size of the circuit becomes large. Especially, recently, there is a demand for forming such a processing circuit on an integrated circuit. In this case, there is the problem that the provision of the correction circuit outside the integrated circuit enlarges the size of the device, while provision inside enlarges the area of the circuit on the chip. It is desired to eliminate these problems in the circuit configuration.
When forming such an image processing circuit for a three-dimensional computer graphic system on an integrated circuit, it is desired to perform the product summation operation using such a linear interpolation processor. Until now, however, two stages have been used—a part for calculating the product and a part for calculating the sum—and therefore two processors are required. Therefore, it has been desired to make improvements in the circuit size and processing speed.
SUMMARY OF THE INVENTION
An object of the present invention is to processing apparatus for linear interpolation perform operations for obtaining original data suitable even when the interpolation coefficient &agr;=1.0, which can perform a product summation operation at a high speed, and which is suited for formation on an integrated circuit without increasing the size of the circuit much at all.
Another object of the present invention is to provide an image processing apparatus which uses such a processing apparatus and consequently can perform, for example, texture mapping, fogging, highlighting, and other image processing efficiently at a high which is suited for to formation on an integrated circuit.
The present inventors considered the fact that the error explained above was caused since it was attempted to make 0×FF (255) correspond to 1.0 in the value a and theorized that it would be possible to eliminate the error by further adding
A
so that [&agr;+1] became 256. Then, they discovered that addition of
A
was possible by switching the +B term to +A in the basic formula of the circuit shown in
FIG. 5
, that is, [A×&agr;+B×
−
&agr;+B], in the case of &agr;=1.0. They further added a new term for carrying out a product summation operation and invented a processing apparatus capable of performing correction multiplication, processing for linear interpolation, and a product summation operation and an image processing apparatus capable of suitably using the processing apparatus for image processing.
Accordingly to a first aspect of the present invention, there is provided a signal processing apparatus for performing the operation [A×&agr;+B×(1−&agr;)], wherein
A
and
B
are any values of a predetermined bit and &agr; is a coefficient with a value of 0≦&agr;≦1 of a predetermined bit width. The signal processing apparatus then obtains; the upper bits of the result of the operation. The signal processing apparatus includes (1); an added value selecting means for selecting the value
A
as the added value
F
when &agr;=1 and selecting the value
B
as the added value
F
when &agr;≠1; (2) and a processing means for performing the operation [A×&agr;+B×
−
&agr;+F] (where
−
&agr; indicates a bit inversion of &agr;) based on the selected added value
F
.
Preferably, the processing means comprises (1) a partial product generating means for selecting the value
A
when the bit is 1 and selecting the value
B
when the bit is 0 for each bit of the coefficient a and generating a partial product by shifting the selected value to a position corresponding to the bit of the &agr;; and (2) an adding means for adding the selected added value
F
and the generated partial products of the number of bits of the &agr;.
Preferably, the adding means is configured by a Wallace-tree type architecture comprised of one-bit adders in a tree structure.
According to a second aspect of the invention, there is provided a signal processing apparatus for performing the operation [A×&agr;+B×(1−&agr;)+C], where
A
,
B
, and
C
are any values of a predetermined bit width and &agr; is a coefficient with a value 0≦&agr;≦1 of a predetermined bit width, and for obta
Horioka Toshio
Iida Ryohei
Chung Daniel J
Kananen Ronald P.
Luu Matthew
Rader & Fishman & Grauer, PLLC
Sony Corporation
LandOfFree
Signal processing apparatus and image processing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal processing apparatus and image processing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal processing apparatus and image processing apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2863536