Signal processing and memory arrangement

Details Signal processing and memory arrangement Signal processing and memory arrangement

1974-11-11

1980-06-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365 45, 365183, 307221C, 357 24, G11C 1140

Patent

active

042098521

ABSTRACT:
An improved arrangement is provided for processing analog and digital signals, where particular advantages are obtained using charge coupled devices (CCDs). A memory arrangement utilizes a novel refresh circuit to re-establish signal amplitudes which are degraded by a CCD memory. Further, various gating and control circuits are used for loading and unloading the memory. A CCD signal processor and memory arrangement is provided for in an embodiment of an array processing system to exemplify one application of these arrangements.

REFERENCES:
patent: 2961535 (1960-11-01), Lanning
patent: 3368203 (1968-02-01), Loizdes
patent: 3643106 (1972-02-01), Berwin
patent: 3701978 (1972-10-01), Miller
patent: 3774169 (1973-11-01), Smith
patent: 3810126 (1977-05-01), Butler
patent: 3868516 (1975-02-01), Buss
patent: 3876989 (1975-04-01), Bankowski
patent: 3889245 (1975-06-01), Gosney
patent: 3891977 (1975-06-01), Amelio
patent: 3909806 (1975-09-01), Uchida
patent: 3914748 (1975-10-01), Barton
patent: 3969705 (1976-07-01), Waggener
patent: 3999171 (1976-12-01), Parsons
IBM Tech. Dis. Bul., "Regeneration Circuit for CLD Shift Register" R. H. Dennard, vol. 14, No. 12, May 1972, pp. 3791-3792.

Affiliated with

Also associated with

Rating

Signal processing and memory arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Signal processing and memory arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal processing and memory arrangement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1483704