Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2000-12-22
2003-07-08
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S765010
Reexamination Certificate
active
06590382
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an apparatus and a method for testing integrated circuits comprising functional circuits and data storage circuits. More particularly, the present invention is directed to a test apparatus and a method for testing an integrated circuit that has a scan-based interface by which data can be shifted through a chain of clocked storage devices and extracted sequentially therefrom to test the device data storage device's input/output (I/O) signal pins for alternating current (AC) defects.
BACKGROUND OF THE INVENTION
The present invention generally relates to integrated circuits containing data storage circuits and functional circuits all of which are coupled to other components, external to the integrated circuit, through signal interface pins. A small number of these signal interface pins are coupled only to the functional circuits and are used to provide necessary control functions, such as clock pulses, test modes, test control data, and etc. to the integrated circuit. The remaining signal interface pins are used to transfer data into and out of the data storage circuits contained in the integrated circuit.
At times, a signal interface or input/output pin, used to transfer data into or out of the data storage circuits, will function correctly in a direct current (DC) mode, that is, it will carry the proper current but will have resistive, inductive or capacitive aspects that affect the alternating current (AC) characteristics, i.e., the rise and fall times of signals passing through the pin. These AC characteristics, by delaying or skewing the shift time of these signals, causes the rise or fall time of the signals to be altered, i.e., to be slower than that called for in the circuit specification. To assure the final quality of the integrated circuit such AC defects must be ascertained by rigorous and extensive testing of the integrated circuit.
At the present time, such AC defect testing requires the use of high frequency automated test equipment (ATE) that provides a tester contact for each signal interface pin on the integrated circuit, i.e., for both functional circuit pins and data storage pins.
Testers having sufficient test contacts for large integrated circuits are expensive to purchase and newer integrated circuits are now being introduced with even higher storage data capacity and thus more input/output pins. The introduction of integrated circuits with more input/output pins means that manufacturers must either upgrade their old testers or purchase new testers.
Thus as integrated circuits continue to increase in pin count and become faster, it becomes increasingly expensive for manufacturers to provide automated test equipment that can speedily test the newer, larger signal pin count, integrated circuits.
Therefore, there is a compelling economic reason to extend the life of the present testers by providing a way to utilize presently available test equipment to test the newer, larger storage capacity, integrated circuits.
It also becomes desirable that means be found to test the newer, large storage capacity, integrated circuits with presently available testers.
SUMMARY OF THE PRESENT INVENTION
The present invention is directed to an apparatus and a method of testing of integrated circuits having a high input/output pin count with an automated test equipment (ATE) having fewer contacts than there are input/output pins on the integrated circuit.
The present invention accomplishes this desirable result by providing a unique device interface board (DIB), between the device under test (DUT) and the tester. This device interface board is arranged to provide direct coupling between each respective tester contact in a first set of selected tester contacts and each respective functional circuit pin on the DUT and to further couple each respective remaining test contact to the input/output pins of a respective chain of serially arranged data storage circuits.
In this way, the present invention permits testing of an integrated circuit having a multiplicity of input/output pins greater than the contacts on the tester.
The present invention, by providing an interface for coupling each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal pins and introducing a selected data string into the integrated circuit, tests each data storage device input/output pin in the integrated circuit in sequence even though the number of contacts on the tester is less than the number of input/output pins to be tested.
These objects, features and advantages of the present invention will be further apparent to persons skilled in the art from the following detailed description taken in conjunction with the accompanying drawings wherein:
REFERENCES:
patent: 5253255 (1993-10-01), Carbine
patent: 6058496 (2000-05-01), Gillis et al.
patent: 6072737 (2000-06-01), Morgan et al.
IBM Technical Disclosure Bulletin, vol. 34, No. 4A, pp. 230-232, Sep. 1991, entitled: Latched I/O Ac Test Using A Reduced Pin Boundary Scan Logic Test Method,.
Angelotti Frank W.
Bushard Louis B.
Grady Matthew S.
Strissel Scott A.
Cuneo Kamand
International Business Machines Corp.
Kobert Russell M.
Thornton Francis J.
Walsh Robert A.
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