Signal margin testing system for dynamic RAM

Details Signal margin testing system for dynamic RAM Signal margin testing system for dynamic RAM

1991-09-17

1993-11-23

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Testing

36518911, G11C 700, G11C 2900

Patent

active

052650561

ABSTRACT:
A signal margin testing system is provided for a memory having a word line voltage boosting circuit which uses a test mode decode circuit to selectively disable the word line boosting circuit and then read out data from storage cells in the memory.

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Research Disclosure, May 1987, No. 277, p. 27718, published by Kenneth Mason Publications Ltd, England, article entitled "CMOS Memory Sorted for Yield Versus Reliability" by K. S. Gray et al.

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