Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1998-09-29
2001-07-24
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S027000
Reexamination Certificate
active
06265893
ABSTRACT:
BACKGROUND
The invention relates to signal line drivers.
On circuit boards, increased switching speeds of signals (some in the sub-nanosecond range) transmitted between components have raised various issues, including increased noise, signal reflections, and power consumption by the components. A source of power dissipation by circuit board components (e.g., integrated circuit chips such as processors, microcontrollers, memory devices, gate array chips, application-specific integrated circuit chips, and the like) is from driver circuitry used to drive signal lines between the components.
One common signaling scheme includes GTL (Gunning transceiver logic) circuitry, which are open-drain drivers having external pull-up resistors. GTL driver circuitry reduces power dissipation for chip-to-chip communication by using an output signal swing that is smaller than the signal range of the driver circuitry in the chips. A further benefit of the reduced voltage swing of signals driven by GTL driver circuitry is increased transmission speeds of signals.
A bi-directional GTL signaling scheme is illustrated in
FIG. 5
, which includes a signal line
10
coupled to driver circuitry
12
and
14
located in chips coupled to different points on the signal line
10
. The driver circuitry
12
includes a pull-down N-channel metal oxide silicon (NMOS) transistor
16
and an external pull-up resistor
18
coupled between a termination voltage Vtt and the drain of the transistor
16
. The driver circuitry
14
on the other end similarly includes an NMOS pull-down transistor
20
and an external pull-up resistor
22
. Conventionally, the termination voltage Vtt may be set lower than the available supply voltage of the chip to reduce the amount of output signal voltage swing.
However, as supply voltages to components continue to decrease, a limit is placed on how much lower the termination voltage Vtt can be set. The combination of reduced signal voltage swings and higher signal switching speeds may cause reduced noise margins on signal lines. As a result, increased power savings become difficult.
Another type of signaling circuitry includes source terminated complementary metal oxide silicon (CMOS) circuitry, in which drivers include both P-channel metal oxide silicon field effect transistors (MOSFETs ) and N-channel MOSFETs that drive a signal line. Source termination resistors, placed in series with the signal line, are sized so that the driver output impedance plus the resistance of the resistor matches the signal line impedance. With this topology, the driving waveform is cut in half by the source termination resistor before being sent down the signal line to a high impedance receiver that positively reflects the incident wave to provide a full signal swing. Typically, source terminated CMOS circuitry has lower power consumption over GTL circuitry. However, with source terminated CMOS circuitry, the signal line is left floating when the coupled drivers are inactive, which may result in power loss due to leakage current through partially on transistors. The floating signal line is also unpredictable, as it may float to any voltage when undriven and may even move with noise. Because of unpredictable signal line behavior when a signal line is left floating by source-terminated CMOS circuitry, backwards compatibility with GTL signal drivers is not available, indicating the desirability of a protocol change.
Thus, signal driving circuitry is needed that reduces power consumption while reliably maintaining signal integrity.
SUMMARY
In general, according to an embodiment, circuitry includes first and second drivers that are coupled to a transmission line. The first driver includes a transistor to drive the transmission line to a specified voltage when the first and second drivers are inactive.
Other features will become apparent from the following description and from the claims.
REFERENCES:
patent: 4760292 (1988-07-01), Bach
patent: 4859877 (1989-08-01), Cooperman et al.
patent: 5821767 (1998-10-01), Osaka et al.
patent: 6060905 (2000-05-01), Bickford et al.
Thomas F. Knight, Jr., et al.,A Self-Terminating Low-Voltage Swing CMOS Output Driver, IEEE Journal of Solid-State Circuits (Apr. 1988), vol. 23, No. 2, pp. 457-464.
Howard Johnson et al.,High Speed Digital Design, Prentice-Hall, Inc. (1993), pp. 231-232.
Chang Daniel D.
Intel Corporation
Tokar Michael
Trop Pruner & Hu P.C.
LandOfFree
Signal line drivers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal line drivers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal line drivers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2564224