Static information storage and retrieval – Read/write circuit – Sipo/piso
Reexamination Certificate
2000-05-24
2001-12-04
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Sipo/piso
C365S189040, C710S029000, C710S033000
Reexamination Certificate
active
06327205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to high-bandwidth communication using CMOS integrated circuits, and more particularly to a system for communicating between circuit components.
2. Background of the Invention
Semiconductor integrated circuits used in digital computing and other digital applications often use a plurality of VLSI circuits interconnected by single or multi-segmented transmission lines for binary communication. Conventional transmission lines include traces, which are formed on a suitable substrate, such as a printed circuit board (PCB). In higher performance memory systems, the data is sent as a burst on both edges of the clock to reduce power and increase the peak bandwidth in DDRDRAMs and RDRAMs. To build large and wide data busses, conventional memory systems use multiple DRAM components. However, the variation between the individual DRAM components can be large, especially if different vendors manufacture the components. This limits the operating frequency of these large memory systems.
Further, with the advent of data communication techniques that offer data transfer rates greater than one gigahertz, skew between circuit (e.g., DRAM) components becomes even more troublesome. Examples of data communication techniques offering data transfer rates over one gigahertz are described in the copending patent applications identified above in the cross-reference to the related applications. It will be appreciated that this problem gets worse as the operating frequency of integrated circuits increases according to Moore's Law, without comparable improvement in packaging and printed circuit boards technology.
Thus, there is now a need for a system and method for transmitting, receiving and synchronizing data between multiple DRAM components at high frequency even when the skew between different components is higher than the data rate.
SUMMARY
The system and method enables the capture of incoming signals from different components when the skew between the different components is higher than the signal rate. The system and method use VTR and /VTR to latch the data or the signals from the same group on every edge and combine them with a serial-to-parallel conversion to allow lower frequency operation inside the DRAM core logic. When multiple VTRs are used for wider memory systems, the latching is done with the system clock after the serial-to-parallel conversion, thereby allowing for skew between multiple VTRs.
A system in accordance with an embodiment of the present invention comprises a first port for serially receiving a first signal at a signal rate from a first component; a second port for serially receiving a second signal at the signal rate from a second component; a first serial-to-parallel conversion circuit for performing serial-to-n-bit-parallel conversion of the first signal, n being greater than one; and a second serial-to-parallel conversion circuit for performing serial-to-n-bit parallel conversion of the second signal.
A method in accordance with an embodiment of the present invention includes serially receiving a first signal at a signal rate from a first component; serially receiving a second signal at the signal rate from a second component; performing serial-to-n-bit-parallel conversion of the first signal, n being greater than one; and performing serial-to-n-bit parallel conversion of the second signal.
REFERENCES:
patent: 3737788 (1973-06-01), Lenz
patent: 4247817 (1981-01-01), Heller
patent: 4663769 (1987-05-01), Krinock
patent: 4675558 (1987-06-01), Serrone
patent: 4745365 (1988-05-01), Ugenti
patent: 4792845 (1988-12-01), Judge
patent: 4942365 (1990-07-01), Satterwhite
patent: 4987572 (1991-01-01), Scott
patent: 5023488 (1991-06-01), Gunning
patent: 5105107 (1992-04-01), Wilcox
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5263049 (1993-11-01), Wincn
patent: 5303200 (1994-04-01), Elrod et al.
patent: 5319755 (1994-06-01), Farmwald et al.
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 5363332 (1994-11-01), Murabayashi et al.
patent: 5378946 (1995-01-01), Reime
patent: 5408129 (1995-04-01), Farmwald et al.
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5455831 (1995-10-01), Bartow et al.
patent: 5473575 (1995-12-01), Farmwald et al.
patent: 5473635 (1995-12-01), Chevroulet
patent: 5498985 (1996-03-01), Parle et al.
patent: 5512853 (1996-04-01), Ueno et al.
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5513377 (1996-04-01), Capowski et al.
patent: 5550496 (1996-08-01), Desroches
patent: 5579492 (1996-11-01), Gay
patent: 5590369 (1996-12-01), Burgess et al.
patent: 5606717 (1997-02-01), Farmwald et al.
patent: 5646642 (1997-07-01), Maekawa et al.
patent: 5706484 (1998-01-01), Mozdzen et al.
patent: 5715405 (1998-02-01), McClear et al.
patent: 5774354 (1998-06-01), Ohta
patent: 5796962 (1998-08-01), Fant et al.
patent: 5878234 (1999-03-01), Dutkiewicz et al.
patent: 5887039 (1999-03-01), Suemura et al.
patent: 5925118 (1999-07-01), Revilla et al.
patent: 5928343 (1999-07-01), Farmwald et al.
patent: 5964845 (1999-10-01), Braun et al.
patent: 6084823 (2000-07-01), Suzuki et al.
patent: WO92/17938 (1992-10-01), None
“IEEE Standard For Low-Voltage Differential Signals (LVDS) For Scalable Coherent Interface (SCI)”, IEEE Std. 1596.3-1996, Mar. 21, 1996, XP002106653, Introduction, Contents and pp. 1-30.
4M×18 SLDRAM Preliminary Data Sheet 9/97 from SLDRAM Consortium.
1M×16×4 Banks DDR SDRAM 6/97 from Samsung.
Kim et al. “A 640MB/s Bi-Dimensional Data Strobed,, Double-Data Rate SDRAM with a 40mw DLL Circuit for a 256MB Memory System”, ISSCC98 Digest pp. 158-159 Feb. 1998.
Morooka et al., “Source Synchronization and Timing Vernier Techniques for 1.2GB/s SLDRAM Interface”, ISSCC98 Digest pp. 160-161 Feb. 1998.
B. Lau et al. “A 2.6GB/s/Multi-Purpose Chip-to-Chip Interface”, ISSCC98 Digest pp. 162-163 Feb. 1998.
LVDS I/O (Scalable Coherent Interface Documents) IEEE P1596.3 working-group activity for high-speed signal link interface.
Hyper-LVDS I/O Cells (LSI Logic Product Briefs).
Richard Crisp, “Direct Rambus Technology: The New Main Memory Standard”, Nov./Dec. 1997 issue of IEEE Micro.
Direct RDRAM 64/72Mbit (256K×16/18×16d), “Advance Information” of 64M/72M Direct RDRAM Data Sheet, dated Oct. 2, 1997.
Tamura et al., “PRD-Based Global-Mean-Time Signaling for High-Speed Chip-to-Chip Communications”, ISSCC98 Digest, pp. 164-165 & pp. 430-432; Feb. 1998.
Griffin et al., “A Process Independent 800MB/s DRAM Bytewide Interface Featuring Command Interleaving and Concurrent Memory Operation”, ISSCC98 Digest, pp. 156-157 Feb. 1998.
RamLink, LVDS I/O (Scalable Coherent Interface Documents) IEEE P1596.4 working-group activity for high-speed signal link interface.
Xilinx Application Note: “Using the Virtex SelectIO”, XAPP 133 Oct. 21, 1998 (Version 1.11), 12 pages.
Rambus, Rambus Technology Overview:, including Introduction and The Rambus Solution, Copyright, Feb. 1999, last modified: Feb. 12, 1999, 5 pages.
Jazio, Inc.
Mai Son
Squire Sanders & Dempsey
LandOfFree
Signal latching of high bandwidth DRAM arrays when skew... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal latching of high bandwidth DRAM arrays when skew..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal latching of high bandwidth DRAM arrays when skew... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2600610