Signal generator for generating a delayed clock signal

Details Signal generator for generating a delayed clock signal Signal generator for generating a delayed clock signal

1990-06-20

1992-07-07

Logan, Sharon D.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341101, 377 48, H03M 900, H03B 1900

Patent

active

051286734

ABSTRACT:
A signal generator having a Johnson counter including a plurality of flip-flops having CLOCK inputs to which a clock signal is inputted; a logic gate to which the clock signal and Q outputs of the flip-flops are inputted, the logic gate being constructed such that the clock signal is passed therethrough each time 2n clock pulses of the clock signal occur and that the logic gate outputs its output as a first signal, n representing the number of the flip-flops of the Johnson counter; and delay means for delaying the clock signal by a time corresponding to an input-output delayed time of the logic gate and for outputting the delayed clock signal as a second signal.

REFERENCES:
patent: 4193539 (1980-03-01), Bowman et al.
patent: 4926451 (1990-05-01), Yoshihara et al.

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