Signal flow driven circuit analysis and partitioning technique

Details Signal flow driven circuit analysis and partitioning technique Signal flow driven circuit analysis and partitioning technique

2006-06-13

2008-11-04

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07448003

ABSTRACT:
A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital portion and an analog portion. A signal flow is defined through the analog portion of the circuit netlist. A system for generating a layout for an analog circuit design is also included.

REFERENCES:
patent: 4884036 (1989-11-01), Koyama et al.
patent: 5740347 (1998-04-01), Avidan
patent: 2002/0033706 (2002-03-01), Khazei
Ramadoss et al., “Test Generation for Mixed-Signal Devices Using Flow Graphs”, Jan. 1996, Ninth International Conference on VLSI Design, Proceedings, pp. 242-248.
Olbrich et al., “An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuit”, Mar. 2001, IEEE Design, Automation and Test in Europe Conference and Exhibition, Proceedings, pp. 829.
Sommer et al., “From System Specification To Layout: Seamless Top-Down Design Method for Analog and Mixed-Signal Applications” 2002, IEEE Design, Automation and Test in Europe Conference and Exhibition, Proceeding pp. 884-891.

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