Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-05-25
2002-11-26
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S040000, C326S046000
Reexamination Certificate
active
06486705
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to field programmable gate arrays (FPGAs). In particular, it relates to the implementation of improved architectures and functions within an FPGA.
2. Background of Related Art
A Field Programmable Gate Array (FPGA) is a programmable integrated circuit which provides a customized logic array and functionality to a particular customer.
FIG. 4
depicts a conventional Field Programmable Gate Array (FPGA).
In particular, as shown in
FIG. 4
, an FPGA
400
typically includes four distinct features: configuration memory
406
, input/output (I/O) blocks
408
-
414
, configurable logic blocks
404
, and a routing network
402
between the internal components.
Configuration memory
406
provides access between the elements of the FPGA
400
and one external controlling device (e.g., a programmer). Based on the contents of the configuration memory
406
, various logical functions of the configurable logic blocks
404
are enabled and wired together via a configuration of the routing network
402
. Similarly, certain logic blocks are provided I/O access through various types of I/O devices
408
-
414
, as determined by both the configuration memory
406
and the routing provided by the routing network
402
.
The configuration memory
406
may be, e.g., static RAM (SRAM). The configuration memory bits turn elements or switches on or off in embedded elements of the configurable logic blocks
404
, and establish routing between elements of the FPGA
400
, to define the functionality of the FPGA
400
.
Typically, individual memory bits of the configuration memory
406
define the desired functionality of the FPGA device
400
. These configuration memory bits are conventionally loaded one at a time using data lines and address lines directly to the configuration memory
406
(e.g., SRAM) over an external bus
420
from an external source. All embedded elements are programmed similarly using the same format to the configuration memory
406
.
Other types of configuration memory
406
typically include, e.g., EPROM or EEPROM, anti-fused, fused, or other storage devices, providing either one-time programmability, or multiple reprogrammability. The configuration memory
406
may be formed of one or more types of memory (e.g., SRAM and EEPROM).
The I/O blocks
408
-
414
conventionally provide direct connection between an internal, embedded component of the FPGA
400
, and external devices. The I/O blocks
408
-
414
may be hard-wired and/or configured and routed based on the user-instructed configuration stored in the configuration memory
406
.
The configuration memory
406
is loaded, or programmed, before use of the FPGA
400
. Before the FPGA
400
is configured, no external devices other than the single programming device connected to the external access bus
420
are permitted to communicate with embedded elements of the FPGA
400
(e.g., with the configurable logic blocks
404
).
The routing network
402
is programmably defined by the configuration memory
406
to route signaling between the internal logic blocks of the FPGA. The routing network
402
carries signal traffic between the various internal, embedded components of the FPGA
400
. Some portions of the routing network
402
may be directly connected or hard wired and/or may not be fully programmable by the user.
FPGA devices often include embedded run-time memory
450
in addition to the configuration memory
406
. The embedded run-time memory
450
is accessible until configuration of the FPGA
400
is complete. Moreover, the configuration memory
406
is generally not reprogrammed while the FPGA device
400
is in operation.
FPGA devices
400
are typically programmed using an appropriate configuration and routing software application which inputs a user's particular requirements, and determines a best configuration of the routing of the FPGA
400
by steps generally referred to as “partitioning”, “placing”, and “routing”, to ultimately configure the elements of the FPGA
400
to meet the particular user's needs.
FPSCs, a more recent derivation of an FPGA, combines field programmable logic with ASIC or mask programmed logic into a single device. FPSCs provide the quick time to market and flexibility inherent in FPGAs, the design effort savings inherent from the use of software driven cores, as well as the speed, design density, and economy inherent in application specific integrated circuits (ASICs).
Embedded cores within an FPSC can take many forms. Generally, the embedded cores available within an FPSC are selected from an ASIC library, but customer specific FPSCs may be developed to include one or more custom, proprietary or otherwise unique embedded core supplied by the user.
The present invention relates generally to the way that an FPGA or FPCS dedicated signal distribution network distributes a signal from a source to the sinks of a network.
Each sink of a signal distribution network has a delay from its source. Different sinks in a distribution network may have different delays. Conventional FPGAs and FPSCs adjust individual sink timing in a signal distribution network using undedicated and slow routing resources, causing increased distributed signal injection time, an increase in routing congestion, and extreme sensitivity to system timing.
When the distribution network is formed, there is a fixed time relationship between the different sinks. In a synchronous system, this fixed time relationship restricts performance of the system when the sinks of a signal distribution are flip-flops and the distributed signal is a clock. In accordance with the invention, if any logical path between any two sink flip-flops is longer than the period of the clock signal being distributed, longer logic paths are given more time to meet system requirements without impacting the period of the distributed clock signal and therefore, overall system performance.
As system input/output (I/O) timing requirements increase, it becomes more difficult to meet I/O setup times, hold times, and clock-to out times. Systems using an early distributed clock signal achieve faster I/O clock-to-out times at the expense of I/O input setup time. This setup time expense is reduced or removed by the introduction of the clock delay to the I/O input flip-flops.
There is a need for a signal distribution scheme in an FPGA or FPSC which supports a fast, programmable network distribution scheme.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a distribution network in a programmable device comprises a routing network, and a fractional cycle stealing delay unit associated with at least one route in the routing network. The fractional cycle stealing delay unit introduces a selected delay between embedded elements in the programmable device.
A method of increasing speed through a distribution network of a programmable device in accordance with another aspect of the present invention comprises selecting a desired delay to an embedded element in the programmable device. A delay tap corresponding to the selected desired delay is routed into the embedded element.
A field programmable gate array in accordance with yet another aspect comprises a plurality of cells, and a clock distribution clocking the plurality of cells. The clock distribution includes a cycle stealing unit adapted to enable clock skewing between series paths.
REFERENCES:
patent: 5455931 (1995-10-01), Camporese et al.
patent: 5790838 (1998-08-01), Irish et al.
patent: 6255848 (2001-07-01), Schultz et al.
Andrews William B.
Dunlop Alfred E.
Fishburn John P.
Scholz Harold N.
Lattice Semiconductor Corporation
Le Don Phu
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