Signal converting receiver having constant hysteresis, and metho

Details Signal converting receiver having constant hysteresis, and metho Signal converting receiver having constant hysteresis, and metho

1999-07-09

2000-10-10

Phan, Trong

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 82, 326 86, H03K 1716

Patent

active

061305480

ABSTRACT:
A LVDS receiver (200) converts a differential input signal (15) at an input (201/202, e.g., voltage difference V.sub.1 -V.sub.2) to a single output signal (20) at an output (295). The receiver (200) has a signal distributor (205), first and second transistor pairs (220,210), a combiner (260), and an output trigger (250). The distributor (205) either forwards the differential input signal (15) to the first transistor pair (220) when the common mode portion of the input signal (15, e.g., V.sub.CM =(V.sub.1 +V.sub.2)/2) of the first and second input signal components is in a first magnitude range (e.g., V.sub.CM >V.sub.REF) or to the second transistor pair (210) when the common mode portion is in a second, different magnitude range (e.g., V.sub.CM <V.sub.REF). The transistors of both pairs (210 and 220) are of the same conductivity type. This approach provides substantially constant input transconductances (g.sub.m) over the whole common mode input signal range.

REFERENCES:
patent: 5559448 (1996-09-01), Koenig
patent: 5767698 (1998-06-01), Emeigh et al.
patent: 5977796 (1999-11-01), Gabara
patent: 5977797 (1999-11-01), Gasbarik
patent: 5994921 (1999-11-01), Hedberg
patent: 6072943 (2000-06-01), Gasparik et al.
"Draft Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)", Draft 1.3, Nov. 27, 1995, IEEE P1596.3-1995, pp. 1-34.

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