Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1998-12-03
2002-05-14
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S168000, C711S169000
Reexamination Certificate
active
06389522
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a signal control circuit used in a circuit or device for communicating data, address, control signals via bus between a main processing circuit, such as a central processing unit CPU, and a subsidiary processing circuit, such as a memory circuit or an input-output circuit. More particularly, the present invention relates to a signal control circuit for controlling input/output of data, address, control signals to and from the subsidiary processing circuit.
2. Description of Related Art
Various electronic devices, control devices are provided with a device or system for controlling bus signals such as data, address, and control signals. The bus signal controlling device includes a main processing circuit, such as a CPU, and a subsidiary processing circuit, such as a memory circuit, an input/output circuit. In the bus signal controlling device, the main processing circuit is connected to the subsidiary processing circuit via a bus. The bus signal controlling device controls input/output of bus signals between the main processing circuit and the subsidiary processing circuit.
For example, a data storage device is widely used in computers, printers. The data storage device includes a CPU and a memory circuit, such as a random access memory (RAM), a read only memory (ROM). The CPU and the memory circuit are mounted on a single substrate, and are connected with each other via address bus, data bus, and control signal lines. The data storage device serves to perform data processing operation such as data storage processing between the CPU and the memory circuit. Each set of bus signals, used in the above-described device, is a digital signal constructed from a plurality of bits.
In recent years, in order to improve the performance of the computers printers, the operation speeds and data processing abilities of the main processing circuit and the subsidiary processing circuit are greatly enhanced. The operation speed of the CPU is greatly enhanced. The capacity of the memory circuit is greatly increased.
SUMMARY OF THE INVENTION
When the operation speeds and the data processing abilities of the main processing circuit and of the subsidiary processing circuit are enhanced, the number of bits constituting each set of bus signals, transferred between the main processing circuit and the subsidiary processing circuit, is also increased. Input/output rate of the bus signals between the main processing circuit and the subsidiary processing circuit is also increased.
When the data processing ability of the CPU is enhanced and the capacity of the memory circuit is increased, for example, the number of bits constituting each set of data and each set of address that are transferred between the CPU and the memory circuit is increased. When the operation speed of the CPU is increased and the reading/writing frequency of the memory circuit is increased, the input/output rate of data and address between the CPU and the memory circuit is increased.
When the number of bits constituting each set of bus signals is increased and the input/output rate of the bus signals is increased, bus signals comprised of a large number of bits are repeatedly and frequently transferred between the main processing circuit and the subsidiary processing circuit. Accordingly, bus signals, having the large number of bits, rapidly change in the bus that connects the main processing circuit and the subsidiary processing circuit.
At an instant when a bus signal having a large number of bits rapidly changes, noise will possibly occur within the bus signal. Especially when all of the bits constituting the bus signal simultaneously rise or fall to the same binary state, noise will highly possibly occur in the bus signal. Immediately after a ten-bit address bus signal changes from “0000000000b” to “1111111111b”, for example, noise will possibly occur in the address bus signal. As a result, a non-stable address signal, influenced from the noise, is inputted to the main processing circuit or to the subsidiary processing circuit. The main processing circuit or the subsidiary processing circuit will possibly detect the received inaccurate address bus signal.
Especially when the memory circuit is constructed from dynamic RAM (which will be referred to simply as DRAM hereinafter), the above-described problem occurs highly likely. The DRAM is a memory circuit that can perform data reading/writing operation rapidly. Especially when the DRAM is used in a so-called page mode, the data reading/writing operation can be performed more rapidly. When performing the rapid data reading/writing operation onto the DRAM, if all the bits constituting each set of data or each set of address signal change simultaneously, noise will highly possibly occur in the data or the address signal. It is noted that during the page mode, a row address is first outputted to the DRAM. Thereafter, a plurality of column addresses are successively outputted to the DRAM, whereby a corresponding plurality of addresses in the single page can be designated.
In order to restrain the above-described noise, it is conceivable to construct the circuit substrate, on which the main processing circuit, the subsidiary processing circuit, and the bus are mounted, into a multilayered structure, thereby increasing a thickness of a pattern for a zero (0) volt (ground voltage) and increasing a ground strength of the circuit substrate. When the circuit substrate is thus constructed in the multi-layered structure, however, the cost required for producing the entire device increases.
The noise can be restrained also when the input/output rate of the bus signal between the main processing circuit and the subsidiary processing circuit is decreased. However, this leads to drop in the entire processing speed of the main processing circuit and the subsidiary processing circuit.
In view of the above-described drawbacks, the present invention is attained to provide an improved signal control circuit that enables input/output of bus signals in accuracy and at a high speed through preventing the bus signals from being inaccurately detected even when noise occurs in the bus signals due to simultaneous changes of the bits located therein.
In order to attain the above and other objects, the present invention provides a signal control circuit for outputting, to a subsidiary processing circuit, control signals for controlling input and output of bus signals with respect to the subsidiary processing circuit, the bus signals being transferred or inputted/outputted via a bus between the subsidiary processing circuit and a main processing circuit, the signal control circuit comprising: a comparing portion that compares at least a bit in at least a predetermined portion of a present bus signal, which is transferred between a main processing circuit and a subsidiary processing circuit at a present timing with corresponding at least a bit in at least a predetermined portion of a preceding bus signal, which is transferred between the main processing circuit and the subsidiary processing circuit at a preceding timing; and an output control portion that delays outputting, to the subsidiary processing circuit, a control signal for controlling input and output of the bus signal when the compared result shows that a predetermined difference occurs between the present bus signal and the preceding bus signal.
More specifically, the main processing circuit and the subsidiary processing circuit are connected with each other via bus. Bus signal is outputted and inputted between the main processing circuit and the subsidiary processing circuit. The bus signal may be a digital signal comprised from a plurality of bits. The input/output of the bus signal indicates either one or both of: output of the bus signal from the main processing circuit to the subsidiary processing circuit; and output of the bus signal from the subsidiary processing circuit to the main processing circuit. Representative examples of the main processing circuit include:
Brother Kogyo Kabushiki Kaisha
Elmore Reba I.
LandOfFree
Signal control circuit for controlling signals to and from a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal control circuit for controlling signals to and from a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal control circuit for controlling signals to and from a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2873556