Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-12-14
2004-02-17
Phu, Phoung (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S371000, C370S516000
Reexamination Certificate
active
06693986
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal control apparatus, a transmission system and a signal resynchronization control method, and, more particularly, to a signal control apparatus which controls digital signals, a transmission system which transmits digital signals over a network, such as SONET (Synchronous Optical Network) or SDH (Synchronous Digital Hierarchy), and a signal resynchronization control method which controls resynchronization of signals, such as a clock.
2. Description of the Related Art
Network synchronous transmission systems, such as SONET of North America and SDH used in general foreign countries, have become the mainstream of the recent multiplex communications technology. Transmission apparatuses on those systems perform clock resynchronization control in order to, for example, suppress jittering of clocks and establish bit phase synchronization.
FIG. 10
is a diagram showing the outline of conventional clock resynchronization control. A serial/parallel converting section
101
performs serial/parallel conversion to convert a serial input clock signal to a parallel signal based on a write clock.
A window setting section
201
performs parallel/serial conversion to convert a parallel signal to a serial signal based on a read clock.
The serial/parallel conversion of an input clock signal increases the phase margin, and bits are identified in this state to thereby suppress jittering. The parallel/serial conversion is then performed to convert the resultant parallel signal back to a serial signal to thereby establish bit phase synchronization. Through this processing, the input clock signal that is synchronous with the frequency of the write clock is resynchronized with the frequency of the read clock.
If the phase of the read pulse varies, however, this conventional clock resynchronization control should undesirably read the same data twice or would suffer data slipping.
FIG. 11
is a diagram illustrating the problem of the conventional clock resynchronization control. When a read pulse is located within a window W
1
(a “L” portion) which is generated from a write clock, parallel data A can be read out. The window W
1
guarantees reading over a range of 1 to 7 in terms of the number of memory stages, and the memory stage numbers
0
,
8
and
9
are slip areas.
When the read pulse is positioned approximately at the center of the window W
1
as in the case of a read pulse R
1
in the diagram, stable reading is possible.
If the phase of the read pulse varies and the read pulse is fixed at either end of the window W
1
as in the case of read pulses R
2
and R
3
, however, further phase shifting is likely to cause data slipping.
Network synchronous transmission systems should construct a highly reliable digital network by repressing such data slipping and provide stable clock frequencies.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a signal control apparatus which efficiently prevents the occurrence of data slipping and executes high-quality signal resynchronization control.
It is another object of this invention to provide a transmission system which efficiently prevents the occurrence of data slipping and executes high-quality signal resynchronization control before transmitting signals.
It is a further object of this invention to provide a signal resynchronization control method which efficiently prevents the occurrence of data slipping and executes high-quality signal resynchronization control.
To achieve the above objects, according to one aspect of this invention, there is provided a signal control apparatus for controlling digital signals, which comprises a serial/parallel converting section for performing serial/parallel conversion on an input signal to yield parallel data; a window setting section for setting a small window having a readout guarantee area narrowed at an optimal position at a time of reading the parallel data when an operational state is unstable, and setting a large window having the readout guarantee area widened from the optimal position when the operational state is stable; and a parallel/serial converting section for reading the parallel data based on a read pulse positioned within the readout guarantee area corresponding to the small window or the large window, and performing parallel/serial conversion on the parallel data to yield serial data.
According to another aspect of this invention, there is provided a transmission system for transmitting digital signals over a network, which comprises a plurality of transmission apparatuses each including the signal control apparatus of the first aspect; and a transmission medium for connecting the transmission apparatuses.
According to a further aspect of this invention, there is provided a signal resynchronization control method for executing signal resynchronization control, which comprises the steps of performing serial/parallel conversion on an input signal to yield parallel data; setting a small window having a readout guarantee area narrowed at an optimal position at a time of reading the parallel data when an operational state is unstable; setting a large window having the readout guarantee area widened from the optimal position when the operational state is stable; and reading the parallel data based on a read pulse positioned within the readout guarantee area corresponding to the small window or the large window, and performing parallel/serial conversion on the parallel data to yield serial data.
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Katten Muchin Zavis & Rosenman
Phu Phoung
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