Signal clamp circuitry for analog-to-digital converters

Details Signal clamp circuitry for analog-to-digital converters Signal clamp circuitry for analog-to-digital converters

1991-02-04

1992-01-28

Pellinen, A. D.

Coded data generation or conversion

Converter compensation

341155, 358172, H03M 106, H04N 518

Patent

active

050847007

ABSTRACT:
Clamping circuitry for adjusting the D.C. voltage of a signal which is A.C. coupled to an ADC includes D.C. level adjusting circuitry coupled to the input of the ADC. Logic circuitry, responsive to a single bit of output samples provided by the ADC, provides control signals to the D.C. level adjusting circuitry, to condition the D.C. level adjusting circuitry to adjust the D.C. level of the A.C. signal to a desired value.

REFERENCES:
patent: 3221253 (1965-11-01), Keyes
patent: 4110745 (1978-08-01), Ninomiya
patent: 4410876 (1983-10-01), Sawagata
patent: 4707741 (1987-11-01), Stratton
patent: 4736117 (1988-04-01), Wieser
patent: 4811016 (1989-03-01), Millward et al.
patent: 4859871 (1989-08-01), Kobayashi et al.
patent: 4982191 (1991-01-01), Ohta
patent: 4998106 (1991-03-01), Koga et al.
patent: 5003564 (1991-03-01), Fling

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