Signal balancing between voltage domains

Details Signal balancing between voltage domains Signal balancing between voltage domains

2006-01-10

2006-01-10

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06986116

ABSTRACT:
A method for balancing signals across an IC design having multiple voltage domains. The method uses a voltage tress to balance the signals at the top level above the voltage domains. Then using worst case and best case signal latencies determines the average latency in each voltage domain. Then balancing signals at the other levels of the design by incrementing the latencies in each domain until a target level based on the slowest average latency is reached.

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