Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2001-07-23
2002-10-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S189090, C365S207000, C365S205000, C365S208000, C327S051000
Reexamination Certificate
active
06473343
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal amplification circuit, in particular, to a sense amplification circuit which is used for data read out of a semiconductor memory device.
2. Description of the Background Art
Conventionally, in a non-volatile semiconductor memory device, or the like, a signal amplification circuit is used which amplifies and senses the difference between currents which flow through two input nodes, respectively, so as to carry out data output in accordance with this current difference. In such a signal amplification circuit, detection sensitivity, detection precision, operational speed, power consumption, and the like, are regarded as important from the viewpoint of performance.
FIG. 14
is a circuit diagram showing the configuration of a signal amplification circuit which is used as a sense amplifier in a non-volatile semiconductor memory device according to a prior art.
Referring to
FIG. 14
, the signal amplification circuit
1
according to a prior art amplifies the difference between currents which flow through sense input nodes Ni
1
and Ni
2
, respectively, so as to reflect that difference in the signal level of the output signal DOUT.
The sense input node Ni
1
is electrically connected to a memory cell transistor MCT via a selection gate YG and a bit line BL at the time of data read out. The memory cell transistor MCT has a control gate which is connected to a word line WL and the source and drain thereof are connected to the ground voltage Vss and the bit line BL, respectively.
The threshold voltage of the memory cell transistor MCT changes in accordance with the level of the stored data (hereinafter referred to as “stored data level”). Accordingly, by activating the word line WL to a predetermined voltage, the threshold voltage of the memory cell transistor MCT, that is to say, a current in accordance with the stored data level, can be made to flow through the memory cell transistor MCT. In general, a plurality of memory cell transistors MCT are selected in response to the activation of one word line WL and a current is made to flow, in accordance with the stored data level, through the plurality of corresponding bit lines, respectively.
The selection gate YG turns on in response to the activation of the column selection line YL. Through a selective activation of the column selection line YL in accordance with the column selection result, one of the plurality of memory cell transistors MCT, which have been selected in response to the. activation of the word line WL, is further selected and is connected to the sense input node Ni
1
.
In this manner, in response to the selective activation of the word line WL and the column selection line YL, the selected memory cell transistor MCT is electrically connected to the sense input node Ni
1
.
On the other hand, the sense input node Ni
2
is electrically connected, at the time of data read out, to the reference memory cell transistor MCRT for giving the reference value at the time of data read out. The reference memory cell transistor MCRT has a fixed threshold voltage which becomes the reference.
In the same manner, as in the configuration of the memory cell transistor MCT, a word line WRL, a selection gate YGR, a bit line RBL and a column selection line YRL are arranged in the reference memory cell transistor MCRT. The word line WRL and the column selection line YRL are activated at the time of data read out.
The signal amplification circuit
1
amplifies the difference between currents which are, respectively, made to flow through the sense input nodes Ni
1
and Ni
2
so as to set the signal level of the output signal DOUT.
The signal amplification circuit
1
has an N channel type field effect transistor Ta, a P channel type field effect transistors Tb and Tc which form a current mirror, a diode DC for carrying out a current-voltage conversion and a bias circuit
2
. Hereinafter, in the present specification, N channel type field effect transistors and P channel type field effect transistors are also referred to simply as N type transistors and P type transistors.
In response to an enabling signal /EN
1
which is inputted to the bias circuit
2
, the N type transistor Ta turns on so that the sense input node Ni
1
and the gates of the P type transistors Tb and Tc which form the current mirror are electrically connected.
In response to the turning on of the N type transistor Ta, a memory cell current Icell, which corresponds to the stored data level of the selected memory cell transistor MCT, is made to flow through the current path including power supply voltage Vcc, P type transistor Tb, N type transistor Ta, sense input node Ni
1
, selected memory cell transistor MCT, and ground voltage Vss.
The voltage level of the sense input node Ni
1
is maintained, at least, at the threshold voltage of the N type transistor Td, or more, within the bias circuit
2
by means of the effect of the bias circuit
2
The P type transistor Tc which forms the current mirror with the P type transistor Tb allows the inside current Ic in accordance with the memory cell current Icell to flow through the node Nc. The ratio of the memory cell current Icell to the inside current Ic is determined by the ratio of the current driving performance of the P type transistors Tb and Tc, that is to say, the ratio of the transistor size.
The diode DC is formed of an N type transistor which is connected so as to form a diode and generates a voltage, at the node Nc, in accordance with the inside current Ic, which flows through the node Nc.
The signal amplification circuit
1
further includes a bias circuit
3
, an N type transistor Te, P type transistors Tf and Tg which form a current mirror and a diode DR.
In response to an enabling signal /EN
2
which is inputted to the bias circuit
3
, the sense input node Ni
2
and the gates of the transistors Tf and Tg which form the current mirror are electrically connected.
In response to the turning on of the N type transistor Te, the reference current Iref, which corresponds to the reference memory cell transistor MCRT, flows through the sense input node Ni
2
.
The bias circuit
3
operates in the same manner as the bias circuit
2
and maintains the voltage level of the sense input node Ni
2
at least at the threshold voltage of the transistor Th, or more.
The same configuration as in the memory cell current Icell is provided for the reference current Iref which flows through the reference memory cell transistor MCRT and the P type transistor Tg which forms the current mirror with the P type transistor Tf allows the inside current Ir in accordance with the reference current Iref to flow through the node Nr. The ratio of the reference current Iref to the inside current Ir is determined by the ratio of the current driving performance of the P type transistors Tf and Tg, that is to say, the ratio of the transistor size.
The diode DR is formed of an N type transistor which is connected so as to form a diode in the same manner as in the diode DC and generates a voltage in accordance with the reference current Iref at the node Nr.
The signal amplification circuit
1
further includes a differential amplifier
4
.
The differential amplifier
4
amplifies the voltage difference between the nodes Nc and Nr and sets the signal level of the output signal DOUT within the range between the power supply voltage Vcc and the ground voltage Vss. The configuration of the differential amplifier
4
is generic, of which the detailed description is omitted.
In such a configuration, a memory cell current Icell which flows through the selected memory cell transistor MCT is compared with the reference current Iref which flows through the reference memory cell transistor MCRT so that the output signal DOUT in accordance with the stored data level of the memory cell transistor MCT can be outputted. Accordingly, data read out of a non-volatile semiconductor memory device is possible by using such a signal amplification circuit
1
.
In the signal amplification c
Kai Yoshihide
Nojiri Isao
Ohba Atsushi
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Pham Ly D
LandOfFree
Signal amplification circuit for amplifying and sensing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal amplification circuit for amplifying and sensing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal amplification circuit for amplifying and sensing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3000321