Sidewall treatment for low dielectric constant (low K)...

Details Sidewall treatment for low dielectric constant (low K)... Sidewall treatment for low dielectric constant (low K)...

2001-04-23

2003-02-04

Nguyen, Ha Tran (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S627000, C438S633000, C438S637000, C438S638000, C438S639000, C438S687000, C438S659000, C438S725000, C438S766000, C438S783000

Reexamination Certificate

active

06514844

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for filling contact openings and vias with copper and creating copper interconnections and lines.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects to contacts to active areas, such as N
+
(P
+
) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like. As the size and cross-sectional dimensions of electrical interconnects get smaller, resistance increases and electromigration increases. Increased resistance and electromigration are undesirable for a number of reasons. For example, increased resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor. Additionally, electromigration effects in aluminum (Al) interconnects, where electrical currents actually carry Al atoms along with the current, causing them to electromigrate, may lead to degradation of the Al interconnects, further increased resistance, and even disconnection and/or delamination of the Al interconnects.
The ideal interconnect conductor for semiconductor circuitry will be inexpensive, easily patterned, have low resistivity, and high resistance to corrosion, electromigration, and stress migration. Aluminum (Al) is most often used for interconnects in contemporary semiconductor fabrication processes primarily because Al is inexpensive and easier to etch than, for example, copper (Cu). However, because Al has poor electromigration characteristics and high susceptibility to stress migration, it is typical to alloy Al with other metals.
As discussed above, as semiconductor device geometries shrink and clock speeds increase, it becomes increasingly desirable to reduce the resistance of the circuit metallization. The one criterion that is most seriously compromised by the use of Al for interconnects is that of conductivity. This is because the three metals with lower resistivities (Al has a resistivity of 2.824+10
−6
ohms-cm at 20° C.), namely, silver (Ag) with a resistivity of 1.59×10
−6
ohms-cm (at 20° C.), copper (Cu) with a resistivity of 1.73×10
−6
ohms-cm (at 20° C.), and gold (Au) with a resistivity of 2.44×10
−6
ohms-cm (at 20° C.), fall short in other significant criteria. Silver, for example, is relatively expensive and corrodes easily, and gold is very costly and difficult to etch. Copper, with a resistivity nearly on par with silver, immunity from electromigration, high ductility (which provides high immunity to mechanical stresses generated by differential expansion rates of dissimilar materials in a semiconductor chip) and high melting point (1083° C. for Cu vs. 659° C. for Al), fills most criteria admirably. However, Cu is difficult to etch in a semiconductor environment. As a result of the difficulty in etching Cu, an alternative approach to forming vias and metal lines must be used. The damascene approach, consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25 &mgr;) design rule Cu-metallized circuits.
However, the lower resistance and higher conductivity of the Cu interconnects, coupled with higher device density and, hence, decreased distance between the Cu interconnects, may lead to increased capacitance between the Cu interconnects. Increased capacitance between the Cu interconnects, in turn, results in increased RC time delays and longer transient decay times in the semiconductor device circuitry, causing decreased overall operating speeds of the semiconductor devices.
One conventional solution to the problem of increased capacitance between the Cu interconnects is to use “low dielectric constant” or “low K” dielectric materials, where K is less than or equal to about 4, for the interlayer dielectric layers (ILD's) in which the Cu interconnects are formed using the damascene techniques. However, low K dielectric materials are difficult materials to use in conjunction with the damascene techniques. For example, low K dielectric materials are susceptible to being damaged and weakened during the etching and subsequent processing steps used in the damascene techniques. In particular, the sidewalls of openings such as trenches and/or vias formed in low K dielectric materials are especially vulnerable.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.
In another aspect of the present invention, a device is provided, the device comprising a first conductive structure, and a first dielectric layer above the first conductive structure. The device also comprises a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening formed in a densified portion of the first dielectric layer.


REFERENCES:
patent: 6001745 (1999-12-01), Tu et al.
patent: 6037664 (2000-03-01), Zhao et al.
patent: 6197688 (2001-03-01), Simpson

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