Sidewall spacer structure for self-aligned contact and...

Details Sidewall spacer structure for self-aligned contact and... Sidewall spacer structure for self-aligned contact and...

2006-06-06

2006-06-06

Wilson, Allan R. (Department: 2815)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S774000, C438S637000, C438S640000

Reexamination Certificate

active

07056828

ABSTRACT:
In one embodiment, adjacent conductive patterns are formed overlying a semiconductor substrate. The conductive patterns each have a conductive line and a capping layer. A first spacer formation layer is formed between the adjacent conductive patterns. The first spacer formation layer is formed between the top surface of the capping layer and the bottom surface of the conductive line. A conformal second spacer formation layer is formed on the conductive patterns. A first interlayer insulating layer is formed on the conformal second spacer formation layer. Next, an opening is formed to extend to a portion of the first spacer formation layer, in the first interlayer insulating layer. The portion of the first spacer formation layer is etched, using the second spacer formation layer as an etch mask, to form a single-layer spacer on sidewalls of the conductive patterns, concurrently with a contact hole.

REFERENCES:
patent: 6033981 (2000-03-01), Lee et al.
patent: 6194302 (2001-02-01), Shen
patent: 6245625 (2001-06-01), Gau
patent: 6335279 (2002-01-01), Jung et al.
patent: 6372575 (2002-04-01), Lee et al.
patent: 6380042 (2002-04-01), Huang
patent: 6495889 (2002-12-01), Takahashi
patent: 6764893 (2004-07-01), Lee et al.
patent: 2001/0045666 (2001-11-01), Kim et al.
patent: 2003/0036291 (2003-02-01), Hong et al.
patent: 2004/0014278 (2004-01-01), Lee et al.
patent: 2004/0077145 (2004-04-01), Inoue
patent: 2004/0119170 (2004-06-01), Kim et al.
patent: 10107125 (2001-09-01), None
patent: 2366076 (2002-02-01), None
patent: 2002-88980 (2002-11-01), None
Jaegoo Lee, et al. “A Novel DRAM Technology using Dual Spacer and Mechanically Robust Capacitor for 0.12μm DRAM and beyond” 31stEuropean solid-state device research conference, Nov. 2001 (4 pages).
English language abstract of Korean Publication No. 2002-88980.
English language abstract of German Publication No. DE 10107125 A1.

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