Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
2000-07-28
2002-08-06
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S445000, C438S453000, C438S682000
Reexamination Certificate
active
06429093
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to a method of fabricating a salicide source line in flash memory having shallow trench isolation (STI) structures.
BACKGROUND OF THE INVENTION
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are typically constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductor, semiconductor, and insulator regions formed on the semiconductor substrate.
The density of the microelectronic devices on the semiconductor substrate may be increased by decreasing spacing between each of the various semiconductor devices. The decrease in spacing allows a larger number of such microelectronic devices to be formed on the semiconductor substrate. As a result, the computing power and speed of the semiconductor component may be greatly improved.
FLASH memory, also known as FLASH EPROM or FLASH EEPROM, is a semiconductor component that is formed from an array of memory cells with each cell having a floating gate transistor. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each cell is a floating gate transistor having a source, drain, floating gate, and a control gate. The floating gate uses channel hot electrons for writing from the drain and uses Fowler-Nordheim tunneling for erasure from the source. The sources of each floating gate in each cell in a row of the array are connected to form a source line.
The floating gate transistors are electrically isolated from one another by an isolation structure. One type of isolation structure used is a LOCal Oxidation of Silicon (LOCOS) structure. LOCOS structures are generally formed by thermally growing a localized oxidation layer between the cells to electrically isolate the cells. One problem with the LOCOS structure is that the structure includes non-functional areas that waste valuable space on the semiconductor substrate.
Another type of isolation structure used is a Shallow Trench Isolation (STI). STI structures are generally formed by etching a trench between the cells and filling the trench with a suitable dielectric material. STI structures are smaller than LOCOS structures and allow the cells to be spaced closer together to increase the density of cells in the array. However, STI structures are often not used in FLASH memory due to the difficulty in forming the source line that connects the cells in each row. The source line in FLASH memory utilizing STI structures often has a higher resistance than a corresponding FLASH memory that uses LOCOS structures. The increased electrical resistance reduces the operational performance of the memory.
One method to reduce the resistance of the source line is to form a silicide film on the source line. The difficulty in forming such a low resistance silicide film on the source line is due to the narrow stack spacing and the current sidewall process. Currently, sidewalls are formed by depositing a blanket film of silicon nitride on the surface of the substrate and then performing a blanket anisotropic etch to remove portions of the film. Using current silicon nitride formation processes, the narrow source line between the stacks will be filled with the silicon nitride film during the film deposition and will not be removed during the subsequent etch process. The source line will therefore be covered with silicon nitride preventing the formation of a silicide film. In addition to preventing the formation of a silicide film, the silicon nitride between the stacks will cause increased stress on the wordlines. This increased wordline stress coupled with the increased implant source line dose required to reduce the source line resistance can potentially lead to the formation of source drain shorts. These source drain shorts are a major factor in reducing the yield of current embedded FLASH processes.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a low resistance source line for flash memory using an STI structure and method of construction. The present invention provides a method for forming a salicide source line for flash memory using a STI structure and a novel silicon nitride formation method. The salicide source line forms a low resistivity path that substantially eliminates or reduces problems associated with the prior methods and systems. The method comprises: providing a semiconductor substrate with a plurality of memory devices and at least one isolation structure, said plurality of memory devices each having a gate and a source; etching a portion of said isolation structure thereby exposing a region of said semiconductor substrate beneath said isolation structure; implanting said region of said semiconductor substrate beneath said isolation structure with a first species; forming a blanket silicon nitride film over said semiconductor substrate wherein said silicon nitride film thickness in narrow regions is 30% to 80% of the silicon nitride film thickness in wide regions; etching said blanket silicon nitride film to form sidewall structures and remove said silicon nitride film over said semiconductor substrate beneath said isolation structure; and forming a silicide on said region of said semiconductor substrate beneath said isolation structure.
REFERENCES:
patent: 5210047 (1993-05-01), Woo et al.
patent: 6258648 (2001-07-01), Lee
patent: 6268248 (2001-07-01), Mehrad
Brugler Mercer L.
Mehrad Freidoon
Xia Jie
Brady III W. James
Elms Richard
McLarty Peter K.
Pyonin Adam
Telecky , Jr. Frederick J.
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