Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1996-03-14
1999-08-17
Le, Dieu-Minh T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 18, 714800, G06F 1100
Patent
active
059387734
ABSTRACT:
A plurality of parity bits is generated for serial transmission of a word of data bits, and the plurality of parity bits is modified before transmission to encode a sideband signal. The word of data bits and the plurality of modified parity bits are serially transmitted. In another embodiment, a serially-transmitted code word comprising a word of data bits and a plurality of parity bits is received, wherein the parity bits have been generated by an encoder and transmitted with the data bits. It is determined whether the parity bits were modified by the encoder to encode a sideband signal, and at least one of error detection and error correction is performed using the parity bits.
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Hannah Eric Cabot
Hauck Jerry V.
Intel Corporation
Kinsella N. Stephan
Le Dieu-Minh T.
Murray William H.
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