Side-by-side inverted memory address and command buses

Details Side-by-side inverted memory address and command buses Side-by-side inverted memory address and command buses

2007-03-06

2007-03-06

Myers, Paul R. (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

Reexamination Certificate

active

10935835

ABSTRACT:
Generating a pair of buses, each coupled to a common terminating device, each having a set of address signal lines that are coupled to a separate memory device, and driving one set of address signal lines with an address driven with true logic states while driving the other set of address signal lines with the same address, but driven to opposing logic states, to achieve a greater balance between the quantity of signals across both buses that are driven to a high state versus those that are driven to a low state.

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