Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-01-23
2007-01-23
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S342000, C257S344000, C257S401000
Reexamination Certificate
active
11005635
ABSTRACT:
The on resistance per unit area of integration of a DMOS structure is reduced beyond the technological limits of a mask that is defined based upon the continuity of a heavily doped superficial silicon region along the axis of the elongated source island openings through the polysilicon gate layer in the width direction of the integrated structure. The mask no longer needs to be defined with a width (in the pitch direction) sufficiently large to account for the overlay of two distinct and relatively critical masks. These two masks are the source implant mask and the body contacting plug diffusion implant contact opening mask. Such a constraint of the prior techniques restricting the opening through the polysilicon gate layer to safely ensure an appropriate distance of the body connection plug diffusion dopant profile from the definition edges of the polysilicon is overcome by defining the body connection plug diffusion implant area by way of a mutual orthogonality between two no longer critical masks that may both be defined at minimum linewidth of the fabrication process.
REFERENCES:
patent: 5719421 (1998-02-01), Hutter et al.
patent: 5736766 (1998-04-01), Efland et al.
patent: 5825065 (1998-10-01), Corsi et al.
patent: 6137140 (2000-10-01), Efland et al.
patent: 6538281 (2003-03-01), Croce et al.
patent: 1158583 (2001-11-01), None
Patents Abstracts of Japan, vol. 005, No. 159, Oct. 14, 1981 & JP56088363A (Nec Corp.) Jul. 17, 1981.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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