Shrinkable and highly coupled double poly EEPROM with inverter

Details Shrinkable and highly coupled double poly EEPROM with inverter Shrinkable and highly coupled double poly EEPROM with inverter

2007-11-27

2007-11-27

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257SE21422, C257SE21209

Reexamination Certificate

active

10990066

ABSTRACT:
A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second poly layer. This configuration allows for an area-efficient layout that is easily shrinkable as compared to prior art memory cells. In addition, stacking the control and floating gates results in higher capacitive coupling. The EEPROM cell also includes an access gate, a tunnel capacitor, and at least one inverter. In some embodiments, the EEPROM cell can be advantageously used to configure programmable logic without need for a conloading step.

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U.S. Appl. No. 10/990,173, filed Nov. 15, 2004, Paak.

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