Short-tolerant resistive cross point array

Details Short-tolerant resistive cross point array Short-tolerant resistive cross point array

2000-09-15

2002-09-24

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S100000, C365S148000, C365S158000

Reexamination Certificate

active

06456525

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to data storage devices. More specifically, the present invention relates to a data storage device including a resistive cell cross point memory array.
Magnetic Random Access Memory (“MRAM”) is a non-volatile memory that is being considered for data storage. A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
The memory cells may include spin dependent tunneling (“SDT”) junction devices. The magnetization of a SDT junction device assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1.’ The magnetization orientation, in turn, affects the resistance of the SDT junction device. Resistance of the SDT junction device is a first value R if the magnetization orientation is parallel and a second value R+&Dgr;R if the magnetization orientation is anti-parallel.
The magnetization orientation of a SDT junction device and, therefore, its logic state may be read by sensing its resistance state. However, the memory cells in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other rows and columns. In this regard, the array of memory cells may be characterized as a cross point resistor network.
An SDT junction device has a tunneling barrier that is only a few atoms thick. Controlling the fabrication process to produce such thin barriers for an entire array of memory cells is difficult. It is likely that some of the barriers will be thinner than designed or contain structural defects. If certain memory cells have tunneling barriers that are defective or thinner than designed, those memory cells might be shorted.
If one SDT junction device is shorted, the shorted SDT junction device will be unusable. In an array that does not use switches or diodes to isolate memory cells from one another, the other memory cells in the same column will also be rendered unusable. Thus, a single shorted SDT junction memory cell can cause a column-wide error.
Error code correction could be used to recover data from a complete column of unusable memory cells. However, correcting a thousand or more bits in a single column is costly, both from a time standpoint and a computational standpoint. Moreover, a typical storage device might have more than one column with a shorted SDT junction device.
Therefore, a need exists to overcome the problems associated with shorted SDT junction devices in resistive cell cross point memory arrays.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a memory cell of a resistive cell cross point memory array includes a memory element and a linear resistive element connected in series with the memory element. If the memory element becomes shorted, the shorted memory element will cause a randomized bit error. However, the shorted memory element will not cause a column-wide error.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.


REFERENCES:
patent: 3761896 (1973-09-01), Davidson
patent: 4396998 (1983-08-01), Hunt et al.
patent: 5365476 (1994-11-01), Mukhanov
patent: 5640343 (1997-06-01), Gallagher et al.
patent: 5761110 (1998-06-01), Irrinki et al.
patent: 5764567 (1998-06-01), Parkin
patent: 5883827 (1999-03-01), Morgan
patent: 5991193 (1999-11-01), Gallagher et al.
patent: 6130835 (2000-10-01), Scheuerlein
patent: 6191972 (2001-02-01), Miura et al.

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