Short disturb test algorithm for built-in self-test

Details Short disturb test algorithm for built-in self-test Short disturb test algorithm for built-in self-test

1998-01-09

1999-11-23

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

371 211, G11C 700

Patent

active

059912138

ABSTRACT:
A short disturb test algorithm for built-in self-test is provided. The short disturb test (108) initially writes a background pattern to all cells in a memory array (24). After verifying the background pattern was written, the opposite of the background pattern is written to a single row of the memory array for a fixed time. After that fixed time has elapsed, the original background pattern is written to the row. The memory array is then refreshed and the next row is written to. After all rows have been written to, the memory array (24) is checked for failures.

REFERENCES:
patent: 5661729 (1997-08-01), Miyazaki et al.
patent: 5661732 (1997-08-01), Lo et al.
patent: 5668815 (1997-09-01), Gittinger et al.
patent: 5675545 (1997-10-01), Madhavan et al.
patent: 5771242 (1998-06-01), Adams et al.
patent: 5818772 (1998-10-01), Kuge

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