Short circuit prevention in the manufacture of semiconductor dev

Details Short circuit prevention in the manufacture of semiconductor dev Short circuit prevention in the manufacture of semiconductor dev

1981-04-28

1982-12-14

Massie, Jerome W.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29591, 156643, 156656, 156657, 156662, 357 59, H01L 21283, H01L 21308

Patent

active

043636969

ABSTRACT:
A first level interconnection layer of substantially a given width is formed on an insulating film on a semiconductor substrate. At least two second level interconnection layers, which cross the first level interconnection layer on another insulating layer, are formed. In a step for forming the first level interconnection layer, projections are formed at each side of the first level interconnection layer between the crossings of the second level interconnection layers. The total width of the first level interconnection layer including the width of the projection is larger than the given width. After the second level interconnection layers are formed, the projections of the first level interconnection layer are removed along with any second level interconnection layer material remaining intermediate the second level interconnection layers, thereby to prevent short-circuiting between the second level interconnection layers.

REFERENCES:
patent: 4076575 (1978-02-01), Chang
patent: 4123565 (1978-10-01), Sumitomo et al.
patent: 4142926 (1979-03-01), Morgan
patent: 4172004 (1979-10-01), Alcorn et al.
patent: 4184909 (1980-01-01), Chang et al.
`Tapering of . . . electrodes`, Research Disclosure (4/81), No. 204, pp. 146-148.

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