Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-12-29
2003-12-23
Myers, Paul R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06668298
ABSTRACT:
FIELD
The present invention relates to a high-speed to lower-speed domain shifting technique and more particularly, the present invention relates to a technique for shifting an input signal from a high-speed domain into a lower-speed clock domain.
BACKGROUND
There are many applications in which digital events must be captured at a high speed and then counted and displayed and/or forwarded to additional digital elements for further processing.
For example, network devices, such as hubs, switches, Remote Network Monitors (RNOM) probes might use hardware counters to speed up statics gathering.
Counters or adders might be implemented in the same time domain as the incoming high-speed events. However, circuits such as adders and counters tend to be slower than shift registers and their preferred usage is in a low speed clock domain.
Thus, the circuit frequency can be affected adversely and operation at full speed may not be possible. This problem is particularly relevant when large adders or counters are required.
SUMMARY
An apparatus for shifting an input signal from a high-speed domain to a lower speed domain includes a counting unit for receiving and counting a high-speed clock. A shift register, connected to a first set of latches, receives an input signal and shifts it out to be latched by the first set of latches in accordance with the high-speed clock, a latch input of the first set of latches receiving a first output of the counting unit. A second set of latches is connected to a bitwise adder connected to a third set of latches. The outputs of the first and third sets of latches are input to the bitwise adder. A detector having an output is connected to latch inputs of the second and third set of latches and receives a second output of the counting unit. The detector and the second and third set of latches operate in accordance with a lower-speed clock. The lower speed clock is a submultiple of the higher speed clock. An output of the third set of latches corresponds to the input signal shifted from a higher-speed domain to a lower-speed domain.
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Kenyon & Kenyon
Myers Paul R.
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