Shift register having latch cell operable in serial-in/parallel-

Details Shift register having latch cell operable in serial-in/parallel- Shift register having latch cell operable in serial-in/parallel-

1996-03-22

1998-08-25

Lee, Thomas C.

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

377 69, G06F 500

Patent

active

057992118

ABSTRACT:
A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.

REFERENCES:
patent: 4429300 (1984-01-01), Yamasawa et al.
patent: 4648105 (1987-03-01), Priebe et al.
patent: 5282234 (1994-01-01), Murayama et al.
patent: 5481749 (1996-01-01), Grondalski
patent: 5489901 (1996-02-01), Fukuda et al.
patent: 5721545 (1998-02-01), Poplevine

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