Shift register clock scheme

Details Shift register clock scheme Shift register clock scheme

2000-05-12

2001-08-07

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S189120, C365S240000

Reexamination Certificate

active

06272060

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to data registration prior to memory storage, and particularly to a clock scheme for peak current reduction during power on reset and data shifting.
DISCUSSION OF RELATED ART
Many memory cell arrays, such as serial programmable read only memory (SPROM), use commonly clocked, serially coupled flip-flops, known as a shift register, to store data prior to data storage in parallel into memory cells within a memory array. Data is serially shifted through each flip-flop in the shift register in response to clock signals until the shift register is full. When the shift register is full, then each data output of each flip-flop is stored in a memory cell. This method of data storage is called a shift register system.
FIG. 1
is a schematic diagram of such a conventional shift register system
100
. A data signal QIN represents a serial data stream (e.g., a series of bits applied to an input pin of an integrated circuit). Therefore, at each clock signal, the current value of the QIN data signal corresponds to a data bit within the serial data stream. The QIN data signal is provided to a shift register
101
. Shift register
101
includes commonly clocked, serially coupled flip-flops
102
. A system clock signal SYSCLK and a clock enable signal ENCLK are generated by external circuitry (not shown) and are used to clock flip-flops
102
. As shown in
FIG. 1
, the clock signal CLK received by flip-flops
102
is the logical NAND of the SYSCLK and ENCLK signals and the inverted clock signal CLK# is the inverse of the CLK signal. Each data bit in the serial data stream is serially shifted through flip-flops
102
of shift register
101
until shift register
101
is full.
Specifically, each of flip-flops
102
provide the data signal present at its input terminal D to its output terminal Q when the clock signal CLK is a logic one. This process is called shifting. Each of flip-flops
102
holds constant the data signal present at its output terminal Q when the clock signal CLK is a logic zero. Thus, a series of clock signals shifts a data bit sequentially through shift register
101
. Shift register
101
is full when the first data bit in the QIN data signal reaches the last flip-flop
102
in shift register
101
. When shift register
101
is full, the data at the Q output terminals of flip-flops
102
are stored in memory structure
103
.
As described above, each of flip-flops
102
responds to the CLK signal at the same time. As a result, a shifting operation causes a large spike of current to be drawn as each of flip-flops
102
draws current simultaneously. As the number of flip-flops in shift register
101
increases, the magnitude of this current spike increases. A common number of flip-flops in shift register
101
is 4000.
FIG. 2
is a plot of current over time for 4000 flip-flops in a conventional shift register system during a shift operation. Note both large current spikes at time=156 ns and 173 ns. These current spikes represent the current drawn by the 4000 flip-flops for each shift operation (i.e., transition of the clock signal CLK to a logic one from a logic zero). As described above, the magnitude of these current spikes is proportional to the number of simultaneously clocked flip-flops performing the shift operation. It would be desirable to minimize the peak current spike during such a shift operation.
When shift register system
100
powers on, a power on reset signal (POR) is asserted high. This logic one value of the POR signal causes an initialization operation in which a logic one is forced into the Q output terminal of each flip-flop
102
. As a result, when shift register system
100
powers on, each of flip-flops
102
is initialized to one. For reasons similar to those of the shifting operation described above, flip-flops
102
draw a large spike of current during the initialization operation. Therefore, it is also desirable to minimize the peak current (the current spike) drawn during an initialization operation.
SUMMARY OF THE INVENTION
A shift register clocking scheme is disclosed wherein flip-flops buffering memory data perform shift operations in response to a set of sub-clock signals. Sub-clock signals are multiple clock signals generated in response to a primary (e.g., system) clock signal. The set of sub-clock signals comprises a number (e.g., eight) of nested sub-clock signals formed from a system clock signal or power on reset command signal. Specifically, the rising edge of the first sub-clock signal occurs prior to the rising edge of the second sub-clock signal and the falling edge of the first sub-clock signal occurs after the falling edge of the second sub-clock signal, thereby nesting the second sub-clock signal within the first sub-clock signal.
The flip-flops are divided among a set of shift registers, each shift register being clocked by one of the set of sub-clock signals. As a result of utilizing sub-clock signals, shift operations for each shift register are spread out over a period of time rather than occurring simultaneously in all shift registers. Spreading out the shift operations of the shift registers causes a series of small current draws corresponding to the shift operation of each shift register.
The total amount of current drawn during these spread out shift operations is comparable to the total amount of current drawn in conventional shift register systems having the same number of flip-flops. However, because fewer flip-flops are clocked by a given sub-clock signal in the present invention than by a given clock pulse in conventional memory systems, the peak current drawn during any one shifting operation in the present invention is much less than the peak current drawn in conventional shift register systems. Therefore, the peak current drawn by the present invention during memory operations is minimized.


REFERENCES:
patent: 4771279 (1988-09-01), Hannah
patent: 4777624 (1988-10-01), Ishizawa et al.
patent: 6034910 (2000-03-01), Iwase

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