Shift-register based row select circuit with redundancy for a FI

Details Shift-register based row select circuit with redundancy for a FI Shift-register based row select circuit with redundancy for a FI

1996-03-01

1998-06-16

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Bad bit

36518912, 365221, 365219, G11C 700

Patent

active

057681961

ABSTRACT:
A FIFO (First-In-First-Out) memory includes a main memory array and a main select circuit having a plurality of serially coupled shift registers, each selecting at least one memory location of the main memory array. The FIFO memory also includes a redundant memory array and a redundant select circuit having a plurality of redundant shift registers, each selecting at least one redundant memory location of the redundant memory array. A switching circuit is provided in the FIFO memory that is coupled to each of the shift registers and each of the redundant shift registers. When a memory location of the main memory is found defective, the switching circuit causes a corresponding shift register of the shift registers to be bypassed in the main select circuit and a redundant shift register of the redundant shift registers to be serially coupled into the main select circuit via a last one of the shift registers.

REFERENCES:
patent: 4807191 (1989-02-01), Flannagan
patent: 4961169 (1990-10-01), Matsumura et al.
patent: 5083294 (1992-01-01), Okajima
patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5267205 (1993-11-01), Hamada
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5546347 (1996-08-01), Ko et al.

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