Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-11-01
2004-04-20
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06724361
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a shift register which is preferably applied to, for example, a driving circuit of an image display device, and which makes it possible to miniaturize the driving circuit and also to desirably change the pulse width of an output signal, and also concerns an image display device using such a shift register.
BACKGROUND OF THE INVENTION
Conventionally, in a data signal line driving circuit and a scanning signal line driving circuit of an image display device, shift registers have been widely used so as to provide synchronized timing that is applied upon sampling inputted video image data, or so as to form a scanning signal to be applied to the scanning signal lines.
In the data signal line driving circuit, a sampling signal is generated so as to write video image data derived from a video image signal in pixels through a data signal line. In this case, when a sampling signal has an overlapped portion with a sampling signal from the preceding stage or the succeeding stage, the resulting video image data fluctuates greatly, causing erroneous image data to be outputted to the data signal line. In order to solve the above-mentioned problems, a conventional shift register
101
has a circuit construction, for example, as shown in FIG.
32
.
The shift register
101
, shown in
FIG. 32
, consists of n stages, and each stage is provided with a D-type flip-flop
102
, a NAND circuit
103
, inverters
104
a
and
104
b
and a NOR circuit
105
. To the shift register
101
, two clock signals SCK·SCKB, which have phases different from each other, and a start pulse SSP are inputted.
Each of the clock signals SCK·SCKB is prepared so as to have half the sampling cycle of the inputted video image signal, and in synchronism with the clock signals SCK·SCKB, pulses are successively outputted from the shift registers
101
on the respective stages. With respect to the i-numbered stage (1≦i≦n), an output Qi−1 of the D-type flip-flop
102
on the (i−1)-numbered stage and an output Qi of the D-type flip-flop
102
on the i-numbered stage are inputted to the NAND circuit
103
on the i-numbered stage so that an output signal NSouti is obtained.
Moreover, in order to prevent a sampling signal Si on the i-numbered stage and a sampling signal Si+1 on the (i+1)-numbered stage from overlapping each other, the output signal NSOUTi is not only directly inputted to one of the input terminals of the NOR circuit on the i-numbered NOR circuit
105
, but also inputted to a delay circuit constituted by inverters
104
a
and
104
b
on two steps. Since the output of the delay circuit is inputted to the other input terminal of the NOR circuit
105
, it is possible to shorten the width of the sampling signal S
1
outputted from the NOR circuit
105
on the i-numbered stage.
The same process as described above is carried out on each of the shift registers
101
on the respective stages so that as illustrated in
FIG. 33
, sampling signals S
1
to Sn having no overlapped portions with each other are obtained.
Next, referring to
FIGS. 34 and 35
, an explanation will be given of a conventional shift register
111
installed in a scanning signal line driving circuit.
The scanning signal line driving circuit outputs a scanning signal to each of the scanning signal lines so that video image data is successively written in pixels arranged on a display section. At this time, the pulse output has to be stopped so that the (i+1)-numbered scanning signal is not overlapped with the i-numbered scanning signal or so that a process for refreshing the video image data that has been written on the i-numbered data signal line is carried out.
Therefore, as illustrated in
FIG. 34
, the conventional shift register
111
, installed in the scanning signal line driving circuit, consists of n stages, and each stage is provided with a D-type flip-flop
112
, a NAND circuit
113
and a NOR circuit
114
. Moreover, to the shift register
111
, two clock signals GCK·GCKB, which have phases different from each other, a start pulse GSP and a pulse width control signal PWC are inputted.
In the shift register
111
, pulses are successively outputted from the respective stages in synchronism with the clock signals GCK·GCKB. With respect to the i-numbered stage (1≦i≦n), an output Qi-
1
of the D-type flip-flop
112
on the (i−1)-numbered stage and an output Qi of the D-type flip-flop
112
on the i-numbered stage are inputted to the NAND circuit
113
on the i-numbered stage so that an output signal NOUTi is obtained. The output signals NOUT
1
to NOUTn, thus obtained, are outputted in the same cycles as the respective scanning signals GL
1
to GLn.
In the shift register
111
, the pulse width control signal PWC is further inputted to one of the input terminals of the NOR circuit
114
on each stage. Moreover, to the other input terminal of the NOR circuit
114
on the i-numbered stage is inputted the output signal NOUTi of the-NAND circuit
113
on the i-numbered stage. Consequently, a scanning signal GLi is outputted from the NOR circuit
114
from the i-numbered stage.
The same process as described above is carried out on each of the shift registers
111
on the respective stages so that as illustrated in
FIG. 35
, sampling signals GL
1
to GLn having no overlapped portions with each other are obtained. Therefore, the (i+1)-numbered scanning signal GLi+1 is not overlapped with the i-numbered scanning signal GLi so that a process for carrying out a refreshing process, etc. on video image data that has been written on the i-numbered data signal is provided.
Here, as illustrated in
FIG. 36
, in the above-mentioned D-type flip-flops
102
·
112
, when a signal A is inputted through the D terminal and two clock signals CK·CKB are inputted through the other terminal, a signal B is outputted from the Q terminal.
However, the conventional shift registers
101
·
111
require circuits as shown in
FIGS. 32 and 34
, resulting in a problem of a bulky driving circuit.
In recent years, there have been ever-increasing demands for image display devices having a wider display screen and a narrower frame width with high precision; therefore, it is necessary to make the area of the driving circuit smaller. Moreover, in applications other than image display devices, there are high demands for simplified circuit construction of shift registers.
Moreover, with respect to a conventional shift register used for a data signal line driving circuit, an arrangement as shown in
FIG. 37
is proposed. In the shift register shown in
FIG. 37
, an S clock signal SCK is applied with a cycle half the sampling cycle of the inputted video image signal, and an output of the shift register section P
1
S is successively outputted in synchronism with the clock signal.
With respect to an n-numbered stage of the shift register P
1
S, an output Q
n
on the n-numbered stage (SSR
n
) and an output Q
n−1
on the (n−
1
)-numbered stage (SSR
n−1
) are used in a NAND_S
n
so as to obtain NSOUT
n
.
A sampling signal on the n-numbered stage is allowed to have a narrower sampling signal by using a NOR_Sa
n
which takes NOR between the NSOUT
n
and the sampling pulse width control signal SPWC for controlling the sampling pulse width, so as not to overlap the sampling signal on the (n−1) stage. The same process is carried out on each of the outputs of the shift registers P
1
S so that, as illustrated in a timing chart in
FIG. 38
, a sampling signal having no overlapped portion is obtained. In this case, the pulse width control signal SPWC has a frequency twice the frequency of the S clock signal SCK.
Moreover, with respect to a conventional shift register used for a scanning signal line driving circuit, an arrangement as shown in
FIG. 39
is proposed. In the shift register shown in
FIG. 39
, a scanning signal, writes a video image signal applied to a data signal line on pixels arranged on a display section, is successively outputted. In this case, with respect
Brownlow Michael James
Cairns Graham Andrew
Kaise Yasuyoshi
Kubota Yasushi
Maeda Kazuhiro
Chow Dennis-Doon
Conlin David G.
Edwards & Angell LLP
Penny John J.
Sharp Kabushiki Kaisha
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