Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-11
2004-05-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S307000
Reexamination Certificate
active
06737698
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of capacitors. In particular, this invention relates to shielded capacitor structures in integrated circuits.
BACKGROUND OF THE INVENTION
There are numerous applications for capacitors formed on integrated circuits. In many of these applications, such as with high frequency integrated circuits, metal-to-metal capacitors are often used because they have a number of advantages over other types of capacitors, such as those formed from gate oxide. For example, metal-to-metal capacitors provide a higher quality factor than gate-oxide capacitors, and the quality factor is independent of the dc voltage of the capacitor. Also, metal-to-metal capacitors provide better linearity than gate-oxide capacitors.
Typical prior art metal-to-metal capacitors use parallel plate structures where the vertical distance between the parallel plates is much less than the lateral dimensions of the plates. In this case, fringing electric fields are present at the edges of the capacitor plates, but most of the electric fields are confined to the region between the capacitor plates.
Another type of prior art capacitor takes advantage of the reduced size of intralayer metal spacings. In this type of capacitor, vertically spaced fingers are connected to alternate capacitor nodes to provide a higher capacitance density than parallel plate structures.
FIG. 1
is a perspective side view of a prior art vertical finger capacitor
100
. Note that
FIG. 1
shows the spatial relationship between the capacitor fingers and does not show the remainder of the capacitor or the integrated circuit.
FIG. 1
shows a capacitor
100
formed between nodes A and B (not shown). The capacitor
100
includes a first set of fingers connected to node A and a second set of fingers connected to node B. The capacitor fingers shown in
FIG. 1
are formed in four levels of metal in an integrated circuit. As shown, the fingers alternate between nodes A and B such that each A finger on the second and third levels of metal is surrounded by four neighboring B fingers and each B finger on the second and third levels of metal is surrounded by four neighboring A fingers. This structure provides greatest capacitance density when each finger is made from a minimum-width line of metal and a minimum spacing separates adjacent fingers.
FIG. 2
is a diagram illustrating the electric fields for the capacitor structure shown in FIG.
1
. As shown, significant electric fields are present around the capacitor fingers. There are several disadvantages with prior art capacitors such as the capacitor shown in
FIGS. 1 and 2
. First, the electric fields present around the capacitor can interact with materials present around the fingers and cause loss in these materials, which reduces the quality factor of the capacitor. Second, the capacitance of the capacitor shown in
FIGS. 1 and 2
is difficult to predict because it is impacted by the properties of materials around the fingers, which may be different than the properties of the dielectric present between the fingers.
SUMMARY OF THE INVENTION
An apparatus of the invention is provided for a capacitor structure formed on a semiconductor substrate for providing capacitance between a first node and a second node comprising: one or more layers of conductive strips, said conductive strips in each layer alternately connected to the first and second nodes, and a conductive plate disposed above or beneath the lowest of the one or more layers of conductive strips.
One embodiment of the present invention provides a capacitor structure formed on a semiconductor substrate for providing capacitance between a first node and a second node comprising: one or more layers of conductive strips, each of said conductive strips in each layer being connected to one of the first or second nodes, and a conductive shield disposed adjacent to the capacitor structure for shielding the capacitor structure.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Samavati. Hirad et al., “Fractal Capacitors”, Feb. 6, 1998, pp. 256-257. ISSCC98/Session 16/ TD Advanced Radio Frequency Circuits/Paper FP 16.6 Digest of Technical Papers.
Samavati, Hirad et al., “Fractal Capacitors”, Dec. 1998, pp. 2035-2041, IEEE Journal of Solid-State Circuits, vol. 33, No. 12.
Dupuis Timothy J.
Niknejad Ali M.
Paul Susanne A.
Johnson & Assoc.
Nelms David
Nguyen Thinh T
Silicon Laboratories Inc.
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