Shielded bit line sensing scheme for nonvolatile semiconductor m

Details Shielded bit line sensing scheme for nonvolatile semiconductor m Shielded bit line sensing scheme for nonvolatile semiconductor m

1998-12-09

2000-05-02

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular connection

365 63, 365203, G11C 1604

Patent

active

060580445

ABSTRACT:
A memory incorporates a shield bit line reading system for fixing one of two bit lines disposed adjacent to each other to a shield potential and reading data to the other bit line. Selected bit lines are precharged to a power source potential, and then brought to a floating state. The shield bit lines are fixed to the power source potential. A period in which the power source potential is applied to the selected bit lines and a period in which the power source potential is applied to the shield bit lines are the same. A source line decoder applies the power source potential to sources of NAND cell units connected to selected bit lines and applies a ground potential to sources of NAND cell units connected to shield bit lines. Then, an output of data is produced from the memory cell to the selected bit lines.

REFERENCES:
patent: 5453955 (1995-09-01), Sakui et al.
patent: 5793666 (1998-04-01), Yamazaki
patent: 5886937 (1999-03-01), Jang
patent: 5892715 (1999-04-01), Hirata et al.
patent: 5914903 (1999-06-01), Kanma et al.
Tomoharu Tanaka et al., A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory'; IEEE Journal of Solid-State Circuits, vol. 29, No. 11; Nov. 1994; pp. 1366-1373.
Ken Takeuchi et al.; A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories'; IEEE Journal of Solid-State Circuits, vol. 31, No. 4; Apr. 1996; pp. 602-609.

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