Sharing bandwidth of a single port SRAM between at least one...

Details Sharing bandwidth of a single port SRAM between at least one... Sharing bandwidth of a single port SRAM between at least one...

2008-03-05

2010-06-15

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S022000, C710S026000, C710S027000, C710S110000, C710S305000, C710S306000

Reexamination Certificate

active

07739433

ABSTRACT:
A dual or triple access interface (e.g., hardware and software implementation) allows a CPU and at least one DMA peripheral, e.g., Universal Serial Bus (USB) DMA engine, to transfer data in and/or out of a common single port SRAM by negotiating access requests between the CPU and the DMA peripheral, and then subsequently forms memory cycles to the single port SRAM to satisfy both the CPU's and DMA peripheral's memory access throughput requirements. This allows the CPU and the at least one DMA peripheral to access a shared single port SRAM by time multiplexing granted accesses between, for example, two or three simultaneous memory access requests, thus eliminating the need for a dual port memory.

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System-on-a-Chip Bus Archtecture for Embedded Applications, ARM Limited.
International Search Report for PCT/US2009/035796, mailed Jul. 2, 2009.

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