Sharing a second tier cache memory in a multi-processor

Details Sharing a second tier cache memory in a multi-processor Sharing a second tier cache memory in a multi-processor

2005-04-12

2005-04-12

Elmore, Reba I. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S119000, C711S130000

Reexamination Certificate

active

06880049

ABSTRACT:
A set of cache memory includes a set of first tier cache memory and a second tier cache memory. In the set of first tier cache memory each first tier cache memory is coupled to a compute engine in a set of compute engines. The second tier cache memory is coupled to each first tier cache memory in the set of first tier cache memory. The second tier cache memory includes a data ring interface and a snoop ring interface.

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